纳米工艺抗辐射加固集成电路设计研究

发布时间：2018-04-05 11:43

本文选题：软错误屏蔽　切入点：单粒子瞬态　出处：《合肥工业大学》2017年硕士论文

【摘要】：随着数字集成电路的工艺尺寸不断缩小,电源电压持续降低,电路的节点电容不断减小,电路节点翻转所需要的临界电荷相应减小,单粒子翻转和单粒子瞬态变得愈发严重。同时由于时钟频率的不断上升,组合逻辑中发生单粒子瞬态的概率也在不断上升。所以,设计抗单粒子瞬态和单粒子翻转的集成电路成为急需解决的问题。本文针对纳米工艺集成电路的软错误问题,在研究现有加固锁存器设计的基础上,提出了有效的抗辐射加固锁存器设计方案,本文的主要工作如下:介绍了国内外集成电路抗辐射加固的研究现状,以及辐射环境的背景知识和辐射效应的分类。阐明了集成电路软错误的基本概念,详细分析了单粒子效应的分类、机理及其故障模型。重点分析了单粒子瞬态和单粒子翻转引起集成电路发生软错误的原理以及瞬态故障的建模分析方法。针对单粒子瞬态和单粒子翻转对锁存器的影响,总结了国内外学者提出的锁存器加固方案,并分析了这些加固方案的设计原理,对其优缺点进行了比较。抗单粒子瞬态的设计方法通常是在组合电路后端使用过滤电路。抗单粒子翻转的设计方法有三模冗余、基于C单元的冗余反馈回路和检错纠错等方法。同时抗单粒子瞬态和单粒子翻转的设计方法有时间冗余与硬件冗余的结合,以及包含延迟单元的锁存器。目前已有的加固设计主要集中在防护单粒子翻转,没有考虑单粒子瞬态对电路的影响。在分析已有加固锁存器的基础上,提出了一种基于PTM 45nm工艺模型的抗辐射加固锁存器设计。由一个施密特触发器、三个传输门、三个反相器和三个C单元组成。利用施密特触发器和反相器构建时间冗余,屏蔽从上游组合逻辑传来的单粒子瞬态;三个交叉互锁的C单元中任意一个的输出由其他两个的输出决定,当内部节点受到高能粒子轰击发生逻辑翻转,通过C单元的软错误屏蔽能力来实现内部节点的自恢复,从而达到容忍单粒子翻转的目的。HSPICE的仿真结果表明,与其他的加固设计相比本文的加固设计的面积、延迟、功耗和PDP分别平均下降了 15.84%、10.31%、46.71 %和 37.72%。
[Abstract]:With the continuous reduction of the process size of the digital integrated circuit, the power supply voltage continues to decrease, the node capacitance of the circuit continues to decrease, the critical charge required for the circuit node flipping is reduced accordingly, and the single-particle flip and single-particle transient become more and more serious.At the same time, the probability of single particle transient in combinational logic is increasing because of the rising clock frequency.Therefore, the design of single-particle transient and single-particle flip-resistant integrated circuits has become an urgent problem.In this paper, aiming at the problem of soft errors in nanoscale integrated circuits, an effective design scheme of anti-radiation strengthened latch is proposed on the basis of studying the existing design of strengthened latch.The main work of this paper is as follows: this paper introduces the research status of integrated circuit radiation reinforcement at home and abroad, as well as background knowledge of radiation environment and classification of radiation effect.The basic concept of integrated circuit soft error is expounded, and the classification, mechanism and fault model of single particle effect are analyzed in detail.The principle of soft error caused by single particle transient and single particle flip and the modeling and analysis method of transient fault are analyzed.Aiming at the effect of single particle transient and single particle flip on latch, the reinforcement schemes of latch proposed by domestic and foreign scholars are summarized, and the design principles of these reinforcement schemes are analyzed, and their advantages and disadvantages are compared.Anti-single-particle transient design usually uses filter circuits at the back end of combinational circuits.The design method of anti-single particle flip has three modes redundancy, redundant feedback loop based on C element and error detection and correction methods.The design methods of resisting single particle transient and single particle flipping include the combination of time redundancy and hardware redundancy, as well as latch with delay unit.At present, the existing reinforcement design mainly focuses on the protection of single particle inversion, without considering the effect of single particle transient on the circuit.Based on the analysis of existing strengthened latch, a design of anti-radiation reinforcement latch based on PTM 45nm process model is proposed.It consists of a Schmidt trigger, three transmission gates, three inverters and three C units.Schmitt flip-flop and inverter are used to construct time redundancy to shield single particle transient from upstream combinational logic, and the output of any one of the three interlocking C cells is determined by the output of the other two.When the internal node is bombarded by high energy particles, the logic flip occurs, and the self-recovery of the internal node is realized by the soft error shielding ability of the C unit, and the simulation results show that the single particle flip can be tolerated.Compared with other reinforcement designs, the area, delay, power consumption and PDP of the reinforcement design in this paper are reduced by 15.84% and 37.72%, respectively.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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