短波数字接收机频率合成器的设计和实现

发布时间：2018-04-25 06:19

  本文选题：DDS + PLL　； 参考：《上海师范大学》2015年硕士论文

【摘要】：接收机系统频率合成器的主要功能是给接收机综合基带子系统和接收机射频子系统提供所需的时钟信号和本振信号,频率合成器是现代电子系统的重要组成部分,是决定电子系统性能的关键设备之一。随着现代通信技术的发展,系统对频率合成器提出了越来越多的要求。低相位噪声、高频谱纯度、高捷变速率和高频率分辨率的频率合成器己经成为频率合成技术发展的主要趋势。本课题采用DDS与PLL相结合的混合频率合成技术实现频率合成器,DDS提供PLL的参考输入信号,PLL中的鉴相器芯片内集成有数字可编程的预分频器和分频器,该结构综合了DDS和PLL两者的优点,同时又在很大程度上克服两者的缺点,很好地满足了课题的设计需要。本文首先讲述了频率合成技术的概念,回顾了频率合成技术的发展历程,介绍了在频率合成技术上,国内外的发展现状。然后介绍了DDS与PLL的概念、结构、工作原理等,分析了相位噪声和杂散的主要来源。接着依据课题指标要求,确定设计方案和几个核心芯片,分析方案可行性,并详细讲述了DDS电路及锁相环电路的设计方法,以及PCB制板的规则和电磁兼容性设计。最后对频率合成器的几个主要性能指标的进行了测试。最终的测试结果显示,在41.4MHz-71.4MHz的频率范围内,频率步进为1Hz,相位噪声优于-127d Bc/Hz(±20KHz),杂散优于-55d B,跳频时间≤3ms(1Hz频差),达到了课题性能指标的要求。
[Abstract]:The main function of the frequency synthesizer of the receiver system is to provide the needed clock signal and local oscillator signal to the receiver integrated baseband subsystem and the receiver radio frequency subsystem. The frequency synthesizer is an important part of the modern electronic system. It is one of the key equipments that determine the performance of electronic system. With the development of modern communication technology, frequency synthesizer is required more and more. Frequency synthesizers with low phase noise, high spectral purity, high agility rate and high frequency resolution have become the main trend of frequency synthesis technology. In this paper, a hybrid frequency synthesizer technique, which combines DDS and PLL, is used to realize the integration of digital programmable predivider and frequency divider in the phase discriminator chip of the frequency synthesizer DDS which provides the reference input signal of PLL. The structure combines the advantages of both DDS and PLL, and at the same time overcomes the shortcomings of both to a great extent, and meets the design needs of the subject well. This paper first describes the concept of frequency synthesis technology, reviews the development of frequency synthesis technology, and introduces the development of frequency synthesis technology at home and abroad. Then, the concept, structure and working principle of DDS and PLL are introduced, and the main sources of phase noise and stray are analyzed. Then according to the requirements of the project, the design scheme and several core chips are determined, and the feasibility of the scheme is analyzed. The design method of DDS circuit and PLL circuit, as well as the rules of PCB board making and the design of EMC are described in detail. Finally, several main performance indexes of the frequency synthesizer are tested. The final test results show that in the frequency range of 41.4MHz-71.4MHz, the frequency step is 1 Hz, the phase noise is better than -127 d Bc / Hz (卤20 KHz), the spurious is better than -55 dB, and the frequency hopping time is 鈮，

本文编号：1800106