一种16位Sigma-Delta调制器的研究设计

发布时间：2018-05-05 23:01

本文选题：∑ + -ΔADC　；参考：《辽宁大学》2015年硕士论文

【摘要】：???ADC主要通过过采样技术、噪声整形技术、反馈以及数字滤波技术的运用,来达到提高信噪比与性能的目的,完成了模拟信号到数字信号的高精度转换。它广泛应用于音频领域。本文完成了一种适用于音频的16 bit???ADC调制器的设计。首先,分析与研究了???ADC的原理,通过对???调制器各种结构的对比,根据设计要求,选定2-1MASH结构作为本文设计???调制器的结构。其次,对量化器位数、过采样率加以确定,选择1位量化器,过采样率为128倍,借助Matlab对系统进行建模仿真。再次,讨论了???调制器的各项非理想因素,在Matlab Simulink中对其仿真,为放大器的设计提出了性能指标。最后,在系统设计的基础之上,对???调制器的各个模块部分进行了电路设计,并利用Cadence Spectre加以仿真验证。论文在???调制器设计方面的探索主要包括:(1)使用Matlab对系统建模,优化了系统参数,实现了一个优化的系统结构;(2)通过系统级对非理想因素的分析,确定了运放的性能指标,并以之指导、优化电路结构的设计;(3)采用了一种低功耗、高速的锁存比较器,提高了电路的性能。本文设计的???调制器基于Chrt 0.35μm标准CMOS工艺,信号带宽为20 KHz,过采样率128,采样信号频率5.12 MHz。通过仿真验证表明,本文设计的???调制器SNDR为95.2 d B,有效位数为15.51 bit,满足设计要求。
[Abstract]:Through the application of over-sampling, noise shaping, feedback and digital filtering, ADC achieves the purpose of improving signal-to-noise ratio (SNR) and performance, and completes the high-precision conversion from analog signal to digital signal. It is widely used in audio field. In this paper, a 16 bit???ADC modulator for audio frequency is designed. Firstly, the principle of ADC is analyzed and studied. According to the design requirements, the 2-1MASH structure is selected as the design design of the modulator. The structure of the modulator. Secondly, the quantizer bit number and over-sampling rate are determined, and one quantizer is selected. The over-sampling rate is 128-fold. The system is modeled and simulated by Matlab. Again, discussed? The non-ideal factors of the modulator are simulated in Matlab Simulink, and the performance index is proposed for the design of the amplifier. Finally, on the basis of the design of the system, Each module of modulator is designed and simulated by Cadence Spectre. Is the paper in? The exploration of modulator design mainly includes: using Matlab to model the system, optimizing the system parameters and realizing an optimized system structure. Through the analysis of the non-ideal factors at the system level, the performance index of the operational amplifier is determined and guided. A low power and high speed latch comparator is used to improve the performance of the circuit. The design of this paper? The modulator is based on Chrt 0.35 渭 m standard CMOS technology, the signal bandwidth is 20 kHz, the over-sampling rate is 128, and the sampling frequency is 5.12 MHz. The simulation results show that the design of this paper is very important. The modulator SNDR is 95.2 dB and the effective bit is 15.51 bit, which meets the design requirements.
【学位授予单位】：辽宁大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761

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