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高压SOI LDMOS器件的结构设计与仿真

发布时间:2018-06-03 05:05

  本文选题:LDMOS + SOI ; 参考:《杭州电子科技大学》2017年硕士论文


【摘要】:在这个快速发展的社会中,高压集成电路被广泛的应用在各个领域,而在高压集成电路中,LDMOS(Laterally Diffused Metal Oxide Semiconductor)器件是该电路对高压器件的首选之一。高压集成电路要求在器件尺寸缩小的同时,其击穿电压不会降低甚至会变大。为了达到这种要求,人们主要考虑制作工艺、结构设计和材料开发这三个方面。在本文中,为了提高LDMOS的耐压能力,主要从器件整体结构的设计这一方面出发考虑。由于制作在绝缘层上硅(silicon on insulator,SOI)的器件相对于制作在体硅(bulk silicon)上的器件而言,其性能上具有更多的优点,所以本论文主要探讨SOI LDMOS器件。在本文中,首先概述了SOI技术及其制备方法。然后讲述了整个SOI LDMOS器件的设计方法。最后,在设计SOI LDMOS器件过程中,主要讨论了栅极场板(field plate)的长度与厚度等各种参数对器件性能的影响。该论文提出了在漂移区内有双氧化槽结构的SOI LDMOS器件(Double Oxide Trench SOI LDMOS),即DOT SOI LDMOS。该器件的结构特点是在器件的漂移区上下表面各有一个氧化槽。这种结构的优点在于漂移区上表面的氧化槽结构能够改善漂移区表面的横向电场,从而增大了器件在横向方向上的耐压能力;位于漂移区下表面的氧化槽结构具有积累空穴的作用,能够增大埋氧层上的纵向电场,从而提高LDMOS器件在纵向方向上的耐压能力。研究结果显示,在相同器件尺寸条件下,当DOT SOI LDMOS的沟槽宽度与厚度分别为10μm和3μm时,其击穿电压要比CSOI LDMOS高30.5%。本文还提出了另外一种有N/P埋层结构的SOI LDMOS器件结构。这种器件结构的特点是在漂移区的右下方铺一部分的高掺杂的N埋层或者是在漂移区的左下方铺一部分高掺杂的P埋层。这两种结构均可以改善漂移区内部的RESURF效应,使漂移区内部的电场分布更加均匀,而且还可以使该结构的埋氧层内部电场变大。通过对PBPL/PBNL SOI LDMOS进行仿真与分析,结果表明:相对CSOI LDMOS而言,PBPL SOI LDMOS的击穿电压增加了48%,导通电阻减小了31.7%;而PBNL SOI LDMOS的耐压能力变高了78%,导通电阻变小了13.8%。
[Abstract]:In this rapidly developing society, high voltage integrated circuits are widely used in various fields, and in high voltage integrated circuits, Laterally Diffused Metal Oxide Semiconductor) devices are the first choice for high voltage devices. High-voltage integrated circuit requires that the breakdown voltage will not decrease or even become larger while the device size is reduced. In order to achieve this requirement, people mainly consider three aspects: fabrication process, structure design and material development. In this paper, in order to improve the voltage resistance of LDMOS, the design of the whole device structure is considered. Because the devices fabricated on insulator have more advantages than those fabricated on bulk silicon, this paper mainly discusses SOI LDMOS devices. In this paper, the SOI technology and its preparation methods are first summarized. Then the design method of the whole SOI LDMOS device is described. Finally, in the process of designing SOI LDMOS device, the influence of the length and thickness of the gate field plate on the performance of the device is discussed. In this paper, double Oxide Trench SOI LDMOSs, or DOT SOI LDMOS., are proposed for SOI LDMOS devices with a double Oxide Trench SOI structure in the drift region. The structure of the device is characterized by an oxidation tank on the upper and lower surface of the drift region. The advantage of this kind of structure is that the oxidation tank structure on the surface of drift region can improve the transverse electric field on the surface of drift region, thus increasing the voltage resistance of the device in the transverse direction. The structure of the oxidation tank located on the surface of the drift region has the function of accumulating holes, which can increase the longitudinal electric field on the buried oxygen layer and improve the voltage resistance of LDMOS devices in the longitudinal direction. The results show that when the groove width and thickness of DOT SOI LDMOS are 10 渭 m and 3 渭 m respectively, the breakdown voltage is 30.5% higher than that of CSOI LDMOS under the same device size. Another SOI LDMOS device structure with N / P buried structure is also proposed in this paper. This device structure is characterized by laying a highly doped N buried layer at the lower right of the drift region or a highly doped P buried layer at the lower left side of the drift region. Both of these two structures can improve the RESURF effect in the drift region, make the electric field distribution more uniform in the drift region and increase the electric field in the buried oxygen layer of the structure. The simulation and analysis of PBPL/PBNL SOI LDMOS show that compared with CSOI LDMOS, the breakdown voltage of SOI LDMOS increases by 48 and the on-resistance decreases by 31.7, while the voltage resistance of PBNL SOI LDMOS increases by 78 and the on-resistance decreases by 13.8.
【学位授予单位】:杭州电子科技大学
【学位级别】:硕士
【学位授予年份】:2017
【分类号】:TN386

【参考文献】

相关期刊论文 前2条

1 胡夏融;张波;罗小蓉;李肇基;;Universal trench design method for a high-voltage SOI trench LDMOS[J];半导体学报;2012年07期

2 张彦飞;吴郁;游雪兰;亢宝位;;硅材料功率半导体器件结终端技术的新发展[J];电子器件;2009年03期



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