通信基带芯片模块级验证平台的研究

发布时间：2018-06-06 01:11

本文选题：通信基带 + OVM　；参考：《西安电子科技大学》2016年硕士论文

【摘要】：随着集成电路的高速发展,芯片设计的规模越来越大,功能越来越复杂,导致在电路设计阶段出现缺陷的可能性越来越高,这就对验证提出了更高的要求。此外随着芯片的应用领域越来越广,对设计安全性的要求也越来越高,为了避免设计漏洞可能造成的严重后果,验证的充分性就显得尤为重要。市场对芯片产品的更新换代也越来越快,在大规模的集成电路开发的前端设计流程中,验证工作已经占了总工作量的百分之七十左右。因此,设计高效可行的验证方法对芯片的设计与应用具有重要意义。本文重点研究数字集成电路设计中通信基带芯片模块级验证平台的设计。在OVM验证方法学的基础上,使用System Verilog语言,结合实际应用需求,针对SOC芯片中DebugTrace系统,设计出重用性好、可靠性高、功能具有模块化的验证平台。同时,在本文所设计的验证平台还对Module TB的结构进行了改进,论文根据平台的实际功能,将ovm_env划分成top_env,src_env和fmt_env三个功能,在SUB TB中将所有traceport的接口信号例化,并连接至DUT(待测设计,Design Under Test),通过monitor和scoreboard作检测对比,验证该模块在整个DebugTrace系统中是否工作正常。SUB TB的工作均在同一TB下完成,而非以往,不同traceport有各自的TB验证各自的功能,简化了TB结构,完成了模块级的验证工作。最终通过一个具体的Trace,即RFIF,验证了本文的验证方法缩短了验证时间,实现了功能覆盖测试点的全覆盖,提升了验证平台的复用性、灵活性、稳定性。论文最后在DebugTrace系统的编译环境下,使用基于Makefile配置文件的验证方法,对RFIF进行验证仿真,并对仿真结果进行分析,新方法的仿真时间为11443ns,较之前的17042ns有了明显的缩短,同时功能覆盖率也达到了100%的预期效果。说明本文方法行之有效,达到了设计指标。
[Abstract]:With the rapid development of integrated circuits, the scale of chip design becomes larger and larger, and the functions become more and more complex, which leads to the higher possibility of defects in the circuit design stage, which puts forward higher requirements for verification. In addition, with the increasing application of the chip, the design security requirements are becoming higher and higher. In order to avoid the serious consequences of the design vulnerability, it is particularly important to verify the adequacy of the chip. The replacement of chip products in the market is also becoming faster and faster. In the front-end design process of large-scale integrated circuit development, verification has accounted for about 70% of the total workload. Therefore, the design of efficient and feasible verification method is of great significance to the design and application of the chip. This paper focuses on the design of communication baseband chip module level verification platform in digital integrated circuit design. On the basis of OVM verification methodology, a verification platform with good reusability, high reliability and modularized function is designed for DebugTrace system in SOC chip by using System Verilog language and practical application requirements. At the same time, the structure of Module TB has been improved in the verification platform designed in this paper. According to the actual function of the platform, the ovm_env is divided into three functions, named topSnvsrcenv and fmt_env, and the interface signals of all traceport are exemplified in SUB TB. It is connected to DUTs (Design Under Test Unit). Through monitor and scoreboard, it is verified that the module works properly in the whole DebugTrace system. SUBTB is completed under the same TB, but different traceport has its own function of TB verification. The TB structure is simplified and the module level verification is completed. Finally, through a specific Trace-RFIFI, the verification method of this paper shortens the verification time, realizes the full coverage of the functional coverage test points, and improves the reusability, flexibility and stability of the verification platform. Finally, under the compiling environment of DebugTrace system, the verification method based on Makefile configuration file is used to verify and simulate RFIF, and the simulation results are analyzed. The simulation time of the new method is 11443ns, which is obviously shorter than that of 17042ns before. At the same time, the functional coverage also reached 100% of the expected effect. It shows that the method is effective and reaches the design target.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN407

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