流水线模数转换器后台数字校准算法的研究与实现

发布时间：2018-06-11 12:21

本文选题：模数转换器 + 数字校准　；参考：《合肥工业大学》2016年硕士论文

【摘要】：模数转换器(Analog-to-Digital Converter, ADC)是一种可以将模拟信号转化为数字信号的器件。它是连接模拟信号和数字信号的桥梁,在诸多类型的模数转换器中,具有高速、高精度以及高分辨率等特点的流水线模数转换器被广泛应用于信号处理系统中。如快速以太网、无线通讯系统、数字接收机、数字视频等。然而,随着CMOS工艺尺寸的不断减小和电源电压的逐渐降低,流水线ADC会受到运放有限增益、电容失配等各种非理想因素的影响。这些非理想因素使得模拟电路的设计变得更加困难。因其数字电路系统呈现的高稳定性、良好的可靠性、没有静态功耗和面积小等优点,使得数字校准技术在设计更高性能ADC中变得必不可少。在诸多种类的数字校准技术中,能够大大提高系统速度的后台数字校准技术近年来应用最为广泛本论文通过对流水线ADC的基础架构原理以及各种非理想因素分析的基础上,介绍了一种基于伪随机序列(Pseudo-random sequence, PN)注入相关性信号的后台数字校准算法。用于校正流水线ADC中由于运放有限增益所带来的非线性误差。这种方法是通过在流水线ADC第一级中加入谐波失真函数来模拟增益放大器的有限增益误差,这些非线性影响最后会体现在数字输出编码中。然后利用PN序列的自身相关性和与其他序列的不相关性,对最后的数字输出信号进行误差提取,再对没有经过校准的数字输出信号进行误差补偿达到最后校准的目的。同时本文还对数字校准算法进行了优化,采用分段累加求平均的方法来进行误差系数的提取,进一步减小了电路的复杂程度和提高了系统的速度。通过系统的仿真,本文在l00M采样时钟频率下,输入正弦信号频率为1.01318359375MHz,经过后台数字校准算法的流水线ADC,信号噪声比SNDR由46.87dB提高到76.27dB,无杂散动态范围SFDR由53.66dB提高到了83dB。
[Abstract]:Analog-to-Digital Converter (ADC) is a device that can convert analog signal into digital signal. It is a bridge between analog signal and digital signal. Among many kinds of analog-to-digital converters, pipelined analog-to-digital converters with high speed, high precision and high resolution are widely used in signal processing systems. Such as fast Ethernet, wireless communication system, digital receiver, digital video and so on. However, with the decreasing of CMOS process size and the decreasing of power supply voltage, pipeline ADC will be affected by a variety of non-ideal factors, such as limited gain of operational amplifier, capacitor mismatch and so on. These non-ideal factors make the design of analog circuits more difficult. Because of its high stability, good reliability, no static power consumption and small area, digital calibration technology becomes necessary in the design of ADC with higher performance. In many kinds of digital calibration technology, the background digital calibration technology, which can greatly improve the system speed, has been widely used in recent years. Based on the analysis of the basic architecture principle of pipeline ADC and various non-ideal factors, A background digital calibration algorithm based on pseudo-random sequence (PN) injection correlation signal is introduced. It is used to correct the nonlinear error caused by the limited gain of operational amplifier in pipelined ADC. This method simulates the gain error of gain amplifier by adding harmonic distortion function to the first stage of pipeline ADC. These nonlinear effects will be reflected in the digital output coding finally. Then the last digital output signal is extracted by using the self-correlation of PN sequence and the non-correlation with other sequences, and then the error compensation of the uncalibrated digital output signal is carried out to achieve the purpose of final calibration. At the same time, the digital calibration algorithm is optimized, and the method of piecewise cumulative averaging is used to extract the error coefficient, which further reduces the complexity of the circuit and improves the speed of the system. The simulation results show that the sinusoidal signal frequency is 1.01318359375MHz at 1000M sampling clock frequency. The signal noise ratio is increased from 46.87dB to 76.27dB, and the SFDR without stray dynamic range is raised from 53.66dB to 83dB by the backstage digital calibration algorithm pipeline ADCR.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN792

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