40纳米工艺下中继器的插入方法研究

发布时间：2018-06-17 06:43

本文选题：中继器插入 + 互连线延时　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：集成电路工艺进入到纳米工艺之后,互连线成为影响电路延时的主导因素。为了保证芯片设计能够达到时序收敛的目标,互连线的延时优化就显得格外重要,其中,中继器插入方法是减小互连线延时最常用、最有效的方式之一。本文在40纳米工艺下,以实际工程为依托,针对高性能微处理器芯片物理设计中的互连问题,对中继器插入方法展开了以下研究工作。一、优化点对点互连线延时的中继器插入方法。本文对大量不同线长和不同类型中继器的组合进行了中继器插入方法的实验和分析。分析结果表明,随着中继器驱动倍数的增大,相同长度互连线的延时逐渐变小,但面积和功耗开销随之增大,综合考虑延时、功耗和面积等开销,较优的互连线段长度是200μm~300μm,较优的中继器类型是12倍驱动的反相器单元。二、优化全局互连总线延时的中继器插入方法。本文针对模块间的有限区域内存在大量全局互连总线所引起的延时、串扰及拥塞问题,进行了中继器插入方法的优化和评估,采用交错插入方式对中继器位置进行优化,采用特殊布线规则对并行总线进行优化。实验分析结果表明,该方法有效地降低了局部拥塞和串扰,减小了全局互连线的延时,将互连线的总延时和串扰分别降低了25.4%和21.8%。三、优化多扇出互连网络延时的中继器插入方法。物理设计中存在一些多扇出互连网络,采用EDA工具自动优化可能引起插入的中继器数量过多,从而导致局部单元密度过高及拥塞问题。本文提出一种同时考虑线长和拥塞的中继器插入优化方法,能减少插入的中继器数量,缓解拥塞问题,并优化互连延时。实验分析结果表明,相比于EDA工具自动优化方法,该方法将中继器插入级数减少了8级,路径总延时减少了237ps,单元密度降低了16.7%。
[Abstract]:After the integrated circuit technology enters the nanotechnology, the interconnect has become the leading factor affecting the circuit delay. In order to ensure that the chip design can achieve the goal of timing convergence, the delay optimization of the interconnects is particularly important, in which the repeater insertion method is one of the most commonly used and most effective ways to reduce the interconnect delay. In this paper, 40 Under the nanotechnology, based on the actual engineering, the following research work is carried out on the interconnect method of the high performance microprocessor chip in the physical design of the high performance microprocessor chip. 1, the method of repeater insertion for the point to point interconnect delay. This paper is a repeater for the combination of a large number of different line lengths and different types of repeater. The results show that the time delay of the same length interconnects gradually decreases with the increase of the driver multiplier of the repeater, but the area and power consumption increase, considering the delay, power and area, the better interconnect line length is 200 m~300 mu m, and the better repeater type is 12 times the reverse phase drive. Two, optimizes the repeater insertion method of the global interconnect bus delay. This paper optimizes and estimates the repeater insertion method for the delay, crosstalk and congestion caused by a large number of global interconnection buses within the finite area between the modules, and uses the interlace insertion to optimize the position of the repeater and adopt special cloth. The line rule optimizes the parallel bus. The experimental results show that the method effectively reduces the local congestion and crosstalk, reduces the delay of the global interconnects, reduces the total delay and crosstalk of the interconnects by 25.4% and 21.8%. three respectively, and optimizes the repeater insertion method of the multi sector interconnect network delay. There are some more in physical design. The fan out interconnection network, using the EDA tool to automatically optimize the number of inserted repeater, leads to high local unit density and congestion. In this paper, a repeater insertion optimization method, which considers both the line length and congestion, can be considered to reduce the number of inserted repeater, alleviate the congestion and optimize the interconnect delay. The analysis results show that, compared with the EDA tool automatic optimization method, the method reduces the repeater insertion series by 8, the path total delay is reduced by 237ps, and the cell density is reduced by 16.7%.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN40

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