基于CMOS工艺10GHz压控振荡器的研究设计与实现

发布时间：2018-07-20 14:11

【摘要】：压控振荡器(VCO)作为锁相环(PLL)的关键组成部分,广泛应用于移动电话和导航终端等通信设备中。其功耗、相位噪声、调谐范围等性能参数对整个无线通信系统的性能有着重要的影响。随着无线通信技术的蓬勃发展和微电子技术的进步,VCO已广泛集成在射频集成电路(RFIC)中,CMOS射频集成电路以其成熟的工艺、低功耗、低成本的特点,已经成为射频集成电路的发展趋势。如今RFIC正向着小尺寸、低成本、低功耗、高频率的趋势发展,采用CMOS工艺设计高性能的集成VCO已经成为RFIC中极具挑战性的研究课题,具有重要的现实意义。论文首先介绍了VCO的发展历史和研究现状,分析了VCO的工作原理及实现方式。其次介绍了相位噪声的概念,深入研究了相位噪声的三种主要模型,解释了不同区域的相位噪声成因,总结和对比了相位噪声优化的一些方法。最后提出了一款低相位噪声、高线性度增益LC VCO的设计方法,电路采用可变电容阵列来提高调谐增益的线性度,通过尾电流管噪声优化、大电容滤波等措施来降低相位噪声。本文的LC VCO芯片采用TSMC 0.18um CMOS工艺,利用Cadence软件进行电路设计、版图设计、寄生参数提取和仿真。仿真结果表明输出频率的调谐范围为9.79～10.61GHz,8个子频带的调谐增益变化范围为128-170MHz/V,电源电压1.8V时,电路消耗6.2mA电流。当频率为10.2GHz时,频偏100KHz处的相位噪声为-91.9dBc/Hz,频偏1MHz处的相位噪声为-113.8dBc/Hz。
[Abstract]:Voltage controlled oscillator (VCO), as a key component of PLL, is widely used in mobile phone and navigation terminal. Its power consumption, phase noise, tuning range and other performance parameters have an important impact on the performance of the whole wireless communication system. With the rapid development of wireless communication technology and the progress of microelectronics technology, VCO has been widely integrated into RF integrated circuits (RFIC) with the characteristics of mature technology, low power consumption and low cost. It has become the development trend of RF integrated circuit. Nowadays, RFIC is developing towards small size, low cost, low power consumption and high frequency. The design of integrated VCO with high performance in CMOS process has become a very challenging research topic in RFIC and has important practical significance. Firstly, the development history and research status of VCO are introduced, and the working principle and realization of VCO are analyzed. Secondly, the concept of phase noise is introduced, three main models of phase noise are deeply studied, the causes of phase noise in different regions are explained, and some optimization methods of phase noise are summarized and compared. At last, a design method of low phase noise and high linearity gain LC VCO is proposed. Variable capacitance array is used to improve the linearity of tuning gain, and the phase noise is reduced by tail-current tube noise optimization and large capacitance filtering. The LC VCO chip in this paper adopts TSMC 0.18um CMOS technology. The circuit design, layout design, parasitic parameter extraction and simulation are carried out by using Cadence software. The simulation results show that the tuning range of output frequency is 9.79 Hz 10.61 GHz, the tuning gain range is 128-170 MHz / V, and the output voltage is 1.8 V, the circuit consumes 6.2mA current. When the frequency is 10.2GHz, the phase noise at 100kHz is -91.9 dBc / Hzand the phase noise at 1MHz is -113.8dBc / Hz.
【学位授予单位】：西北大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN752;TN405

【相似文献】