流水线型ADC确定性后台校正系统研究与设计
发布时间：2018-08-13 09:29
【摘要】：模数转换器(Analog-to-Digital Converter,ADC)在混合信号系统中起到将外界模拟信号转换为数字信号的特殊作用。流水线型ADC作为中高速ADC的代表,能对速度、精度和功耗很好地折中,在很多领域都有广泛应用。所以它一直是模拟/混合信号集成电路中的研究热点。随着集成电路工艺的进步,数字电路飞速发展,而模拟集成电路的发展却相对滞后,ADC也就成了限制混合信号系统发展的瓶颈。数字校正技术的出现以及广泛应用使得ADC设计中对模拟信号的精度要求转向数字域。该技术能缓和电源电压降低和晶体管本征增益下降对ADC中模拟电路设计的影响,并且在实现高精度ADC的同时显著降低ADC功耗。与常规的数字辅助校正ADC采用开环工作方式的简单放大器代替传统的闭环运放不同,本文采用了电流效率更高的推挽共源运放。对低增益推挽共源运放引入的高阶非线性误差,本文采用对运放传输函数建立精确模型的方式进行消除。该校正算法首先在流水线子级中引入校正子DAC,通过周期性地向校正子DAC注入数字测试信号获得建模所需的插值端点,然后采用分段的三阶多项式拟合出运放传输函数曲线。针对工艺限制引入的电容匹配误差,本文又采用Karanicolas技术进行校正。为了验证这种算法的校正效果,本文设计了12位分辨率,10M采样率的流水线型ADC核心电路,其中第1-4级子级采用推挽共源运放作为级间运算放大器。ADC核心电路和数字校正算法混合仿真的结果表明,ADC的DNL和INL分别从校正前的(-1~1.75)LSB和(-7.9~7.6)LSB提高到校正后的(-0.75~0.5)LSB和(-0.9~1.2)LSB。对于4.88MHz的正弦测试信号,SFDR和SNDR分别由校正前的44.3d B和38.8d B提高到校正后的82.0d B和70.7d B。校正后ADC的有效位数从6.2位提高到了11.5位。该ADC的总功耗为89.5m W,数字电路占总功耗的10.0%。同时,该校正算法只需要11264个采样周期即可完成所有校正参数估计,具有收敛时间短的特点。
[Abstract]:Analog-to-Digital converter plays a special role in converting external analog signal into digital signal in mixed signal system. Pipelined ADC, as the representative of medium and high speed ADC, can make a good compromise on speed, precision and power consumption, and has been widely used in many fields. Therefore, it has always been the research hotspot in analog / mixed signal integrated circuits. With the progress of integrated circuit technology, digital circuits are developing rapidly, but the development of analog integrated circuits is relatively lagging behind ADC has become a bottleneck limiting the development of mixed signal systems. With the emergence and wide application of digital correction technology, the precision of analog signal in ADC design is changed to digital domain. This technique can alleviate the influence of the decrease of power supply voltage and transistor intrinsic gain on the design of analog circuits in ADC, and reduce the power consumption of ADC while realizing high precision ADC. Different from the conventional digital auxiliary correction (ADC), which uses a simple amplifier with open loop operation mode instead of the traditional closed-loop operational amplifier, this paper uses a push-pull common-source operational amplifier with higher current efficiency. The high order nonlinear error caused by low gain push-pull common-source operational amplifier is eliminated by establishing an accurate model of the transmission function of the amplifier. The correct algorithm first introduces the corrector DAC into the pipeline sublevel and periodically injects the digital test signal into the corrector DAC to obtain the interpolation endpoint needed for modeling. Then the piecewise third-order polynomial is used to fit the operational amplifier transfer function curve. Aiming at the capacitance matching error caused by process limitation, Karanicolas technique is used to correct the error. In order to verify the correction effect of this algorithm, a pipelined ADC core circuit with 12 bit resolution and 10 M sampling rate is designed. In the 1-4 sub-stage, the push-pull common-source operation amplifier is used as the core circuit of the interstage operational amplifier. The simulation results show that the DNL and INL of the ADC are improved from (-1) 1.75 LSB and (-7.97. 6) LSB before correction to (-0.75 ~ 0.5) LSB and (-0.91.2) LSBs after correction, respectively. SFDR and SNDR for 4.88MHz are increased from 44.3 dB and 38.8 dB before correction to 82.0 dB and 70.7 dB after correction, respectively. After correction, the effective bit number of ADC is increased from 6.2 bit to 11.5 bit. The total power consumption of the ADC is 89.5m W, and the digital circuit accounts for 10.0% of the total power consumption. At the same time, it only needs 11264 sampling periods to estimate all the corrected parameters, which has the advantage of short convergence time.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
本文编号：2180574
[Abstract]:Analog-to-Digital converter plays a special role in converting external analog signal into digital signal in mixed signal system. Pipelined ADC, as the representative of medium and high speed ADC, can make a good compromise on speed, precision and power consumption, and has been widely used in many fields. Therefore, it has always been the research hotspot in analog / mixed signal integrated circuits. With the progress of integrated circuit technology, digital circuits are developing rapidly, but the development of analog integrated circuits is relatively lagging behind ADC has become a bottleneck limiting the development of mixed signal systems. With the emergence and wide application of digital correction technology, the precision of analog signal in ADC design is changed to digital domain. This technique can alleviate the influence of the decrease of power supply voltage and transistor intrinsic gain on the design of analog circuits in ADC, and reduce the power consumption of ADC while realizing high precision ADC. Different from the conventional digital auxiliary correction (ADC), which uses a simple amplifier with open loop operation mode instead of the traditional closed-loop operational amplifier, this paper uses a push-pull common-source operational amplifier with higher current efficiency. The high order nonlinear error caused by low gain push-pull common-source operational amplifier is eliminated by establishing an accurate model of the transmission function of the amplifier. The correct algorithm first introduces the corrector DAC into the pipeline sublevel and periodically injects the digital test signal into the corrector DAC to obtain the interpolation endpoint needed for modeling. Then the piecewise third-order polynomial is used to fit the operational amplifier transfer function curve. Aiming at the capacitance matching error caused by process limitation, Karanicolas technique is used to correct the error. In order to verify the correction effect of this algorithm, a pipelined ADC core circuit with 12 bit resolution and 10 M sampling rate is designed. In the 1-4 sub-stage, the push-pull common-source operation amplifier is used as the core circuit of the interstage operational amplifier. The simulation results show that the DNL and INL of the ADC are improved from (-1) 1.75 LSB and (-7.97. 6) LSB before correction to (-0.75 ~ 0.5) LSB and (-0.91.2) LSBs after correction, respectively. SFDR and SNDR for 4.88MHz are increased from 44.3 dB and 38.8 dB before correction to 82.0 dB and 70.7 dB after correction, respectively. After correction, the effective bit number of ADC is increased from 6.2 bit to 11.5 bit. The total power consumption of the ADC is 89.5m W, and the digital circuit accounts for 10.0% of the total power consumption. At the same time, it only needs 11264 sampling periods to estimate all the corrected parameters, which has the advantage of short convergence time.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
【参考文献】
相关期刊论文 前1条
1 殷秀梅;魏琦;许莱;杨华中;;A low power 12-b 40-MS/s pipeline ADC[J];半导体学报;2010年03期
，本文编号：2180574
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