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10位低功耗SAR结构ADC的研究与设计

发布时间:2018-08-17 16:49
【摘要】:模数转换器(Analog to Digital Converters,ADC)是连接模拟信号和数字信号的桥梁。随着数字信号处理技术的快速发展,模数转换器得到非常广泛的应用。逐次逼近型模数转换器(Successive Approximation Register,SAR)由于其芯片面积小,转换精度高,且能够达到较高的采样速率等优点,近些年来已逐渐成为各大高校、研究所、以及企业的研究热点。通常,逐次逼近模数转换器(SAR ADC)广泛应用于低功耗、低速(低于10MS/s)邻域。近年来,随着CMOS器件的特征尺寸的不断缩小,器件速度的提高,5至10位SAR ADC的采样率达到几十MS/s到几个GS/s。SAR ADC的特点是低功耗和低成本,在一些便携式设备或低功率领域具有更强的吸引力。本文展现10位40MS/s的逐次逼近模数转换器(SAR ADC)的研究与设计。提出了一种新的异步控制结构。为了降低功耗,使用单调型电容开关算法。为了提高ADC的线性度,使用两相不交叠时钟。为了提高比较速度,比较器中加入多余的MOS晶体管。在0.18μm 1P6M CMOS工艺下,采用1.8V的电源,输入频率16.6525MHZ下的动态性能,40MS/s的SAR ADC的功耗仅为0.776mW,版图面积0.77736mm~2,对应的信号失真比SNDR为59.9dB,无杂散动态范围SFDR为68.5dB。
[Abstract]:Analog-to-digital converter (Analog to Digital converter) is a bridge between analog signal and digital signal. With the rapid development of digital signal processing technology, A-D converter is widely used. Because of its small chip area, high conversion precision and high sampling rate, successive approximation analog-to-digital converter (Successive Approximation) has become a research hotspot in universities, research institutes and enterprises in recent years. In general, successive approximation analog-to-digital converter (SAR ADC) is widely used in low power consumption, low speed (lower than 10MS/s) neighborhood. In recent years, with the continuous reduction of the characteristic size of CMOS devices, the improvement of device speed, the sampling rate of 5 to 10 bits SAR ADC can reach tens of MS/s to several GS/s.SAR ADC, which is characterized by low power consumption and low cost. More attractive in some portable devices or low power areas. This paper presents the research and design of a 10 bit 40MS/s successive approximation A / D converter (SAR ADC). A new asynchronous control structure is proposed. In order to reduce power consumption, the monotonic capacitor switch algorithm is used. In order to improve the linearity of ADC, two-phase non-overlapping clock is used. In order to improve the speed of comparison, extra MOS transistors are added to the comparator. Under 0.18 渭 m 1P6M CMOS process, the dynamic performance of 40 Ms / s SAR ADC with input frequency 16.6525MHZ is only 0.776 MW, the layout area is 0.77736 mm / 2, the corresponding signal distortion ratio is 59.9 dB, and the SFDR is 68.5 dB with a 1.8 V power supply.
【学位授予单位】:南京邮电大学
【学位级别】:硕士
【学位授予年份】:2017
【分类号】:TN792

【参考文献】

相关期刊论文 前2条

1 袁小龙;赵梦恋;吴晓波;严晓浪;;低功耗高精度逐次逼近型模数转换器的设计[J];浙江大学学报(工学版);2006年12期

2 殷勤;戚韬;吴光林;吴建辉;;多通道逐次逼近型10bit 40Ms/s模数转换器的设计[J];电子器件;2006年04期



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