基于0.18um CMOS工艺的时间数字转换器的设计与实现

发布时间：2018-08-18 17:53

【摘要】：随着集成电路的不断发展,越来越多的混合信号电路和模拟集成电路采用数字辅助单元来完成电路的设计,如在模数转换器中采用数字校准模块,更有些将电路的大部分功能数字化,如全数字锁相环。数字集成电路对时间域的信号具有良好的处理能力,时间数字转换器(TDC)作为模拟连续时间信号与数字离散信号之间的桥梁,也开始被用来构建一些模拟集成电路。此外,在高能物理和粒子物理领域中,TDC是高精度时间间隔测量系统的核心单元。因此,TDC的研究对于集成电路设计和高精度测量都有重要意义。本论文主要研究高速高精度时间数字转换器,基于TSMC 0.18μm CMOS工艺,采用全定制和半定制相结合的方法,完成电路的设计与实现。为了实现低于门延时的精度,在比较各种高精度TDC结构以及它们的优缺点之后,选择以游标型TDC为原型,整个电路由三部分构成：双通道游标延时线电路以及读出电路和编码电路。其中,游标延时线电路采用全定制方法设计,主要实现延时单元延时值的精确控制；读出电路和编码电路采用半定制方法设计,前者主要完成温度计码的暂存和对齐,后者则采用流水线结构以保证500MHz的转换速度。这种数模混合设计方法在保证电路性能的同时,也降低了电路的设计难度。为了方便芯片测试,在芯片中还设计了内嵌激励信号模块,该模块通过全定制方法设计,能够产生若干组均匀分布在整个动态范围之中的时间间隔。所设计的TDC芯片已完成了后仿真、流片和测试,整体版图面积为1.25×0.675mm2。测试结果表明,该TDC芯片能够满足设计指标,在500MHz方波信号和1.8V电源电压下总的电流为66.2mA。基于测试结果,论文还进一步研究分析了提高游标型TDC性能的方法,并采用减小单级延时线长度的方法设计了基于层次结构的高性能TDC,该TDC由第一级延时单元和第二级高精度TDC构成,其中高精度TDC包含四路16级游标延迟线电路。该TDC整体版图面积为0.735×0.92mm2,后仿真结果表明,高性能TDC性能达到指标要求,且面积和功耗有一定程度的改进。
[Abstract]:With the continuous development of integrated circuits, more and more mixed signal circuits and analog integrated circuits use digital auxiliary units to complete the circuit design, such as the use of digital calibration modules in analog-to-digital converters. Some digitize most of the functions of the circuit, such as all-digital phase-locked loops. Digital integrated circuit (DIC) has good processing ability for time domain signal. As a bridge between analog continuous time signal and digital discrete signal, time digital converter (TDC) has been used to construct some analog integrated circuits. In addition, in the field of high energy physics and particle physics, TDC is the core unit of high precision time interval measurement system. Therefore, the research of TDC is very important for IC design and high precision measurement. In this paper, the high speed and high precision time digital converter is studied. Based on TSMC 0.18 渭 m CMOS technology, the circuit is designed and implemented by the combination of full customization and semi-customization. In order to achieve the accuracy lower than the gate delay, after comparing various high-precision TDC structures and their advantages and disadvantages, the Vernier TDC is chosen as the prototype. The whole circuit consists of three parts: double channel Vernier delay line circuit, readout circuit and coding circuit. Among them, the Vernier delay line circuit is designed by full-custom method, which mainly realizes the accurate control of delay value of delay unit, and the readout circuit and coding circuit are designed by semi-custom method, the former mainly completes the transient storage and alignment of thermometer code, The latter adopts pipeline structure to ensure the conversion speed of 500MHz. This method not only ensures the circuit performance, but also reduces the difficulty of circuit design. In order to facilitate the chip test, the embedded excitation signal module is designed in the chip. The module can produce several groups of time interval evenly distributed in the whole dynamic range by the method of full customization. The designed TDC chip has completed post-simulation, streaming and testing, and the overall layout area is 1.25 脳 0.675mm-2. The test results show that the TDC chip can meet the design requirements and the total current is 66.2 Ma under the 500MHz square wave signal and 1.8 V power supply voltage. Based on the test results, the methods to improve the performance of Vernier TDC are further studied and analyzed. The high performance TDC based on hierarchical structure is designed by reducing the length of single stage delay line. The TDC is composed of the first stage delay unit and the second stage high precision TDC. The high precision TDC contains four 16-stage Vernier delay line circuits. The overall layout area of the TDC is 0.735 脳 0.92mm2.After the simulation results show that the performance of the high performance TDC meets the requirements, and the area and power consumption are improved to a certain extent.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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