基于过零检测技术的Pipelined ADC研究

发布时间：2018-08-23 10:24

【摘要】：数字化是当今频繁提及的话题,工艺的进步促使数字系统的集成度越来越高,数据处理速度越来越快。巨大的性能优势使得许多模拟信号处理工作被数字技术所取代。然而自然界产生的信号,如声音、光、温度、压力等,皆是模拟的方式变化的。作为模拟域与数字域的接口,模数转换器的地位仍旧不可取代,但系统对模数转换器的速度要求大幅提高,同时便携式设备与智能设备的普及使得业界越发强调系统的低功耗设计。在此背景下,国内外高校和公司提出了许多高速低功耗模数转换器结构。其中基于过零检测技术的流水线模数转换器不仅在系统架构上保留了流水线模数转换器高速高精度的优点,而且在单级电路中采用低功耗的过零检测器和受控电流源替换高功耗的运算放大器,大大降低了系统功耗。并且由于不存在反馈环路,解决了系统稳定性的问题,简化了设计,也减轻了工艺变化对系统的影响。本文在55nm CMOS工艺下,完成了一款电源电压2.5 V,分辨率10位,采样速率50 MSPS的基于过零检测技术的流水线模数转换器的设计。整个系统共包含10级,其中1级采样保持模块,8级1.5位的子模数转换器和1级2位的并行模数转换器。为了提高动态范围和线性度,系统采用全差分结构。过零检测功能主要依靠一个五管运算放大器完成,并在过零检测器中加入延迟调节单元用以修正工艺、温度等因素造成的延迟变化。采用改进的共源共栅电流镜,降低了电流镜关断时对输出端的电荷注入。使用改进的过零检测器作为并行模数转换器的比较单元,在采样相即可完成对输入信号的量化与编码,增大了MDAC在保持相中可用的残差放大时间。采用失调误差前台校正与失调误差后台校正相结合的方式来修正系统中非理想因素引入失调误差,可有效削减模数转换器输出动态性能中的静态能量。在采样频率为50 MSPS,输入信号为频率16.89 MHz弦波信号的仿真条件下,模数转换系统的性能为信号噪声失真比约为59 dB,无杂散动态范围约为67 dB,有效位数约为9.5位,模数转换器的核心功耗约为27.5 mW。
[Abstract]:Digitization is a topic frequently mentioned nowadays. The progress of technology makes the integration of digital system more and more high and the speed of data processing faster and faster. Great performance advantage makes many analog signal processing work replaced by digital technology. However, the signals produced by nature, such as sound, light, temperature, pressure and so on, are changed in a simulated way. As the interface between analog domain and digital domain, A / D converter is still irreplaceable, but the speed of ADC is greatly improved. At the same time, the popularity of portable devices and smart devices makes the industry pay more attention to the low power design of the system. In this context, universities and companies at home and abroad have proposed many high-speed low-power A-D converter structures. The pipelined A / D converter based on zero crossing detection technology not only retains the advantages of high speed and high precision in the system architecture, but also has the advantages of high speed and high precision. Moreover, the low power zero crossing detector and controlled current source are used to replace the high power operational amplifier in the single stage circuit, which greatly reduces the power consumption of the system. Because there is no feedback loop, the problem of system stability is solved, the design is simplified, and the influence of process change on the system is alleviated. In this paper, a pipelined analog-to-digital converter based on zero-crossing detection technology is designed based on 55nm CMOS technology, which has a power supply voltage of 2.5 V, a resolution of 10 bits and a sampling rate of 50 MSPS. The whole system consists of 10 stages, of which one stage sampling and holding module is 8 stage 1.5 bit sub A / D converter and 1 stage 2 bit parallel A / D converter. In order to improve the dynamic range and linearity, the system adopts a fully differential structure. The function of zero-crossing detection mainly depends on a five-transistor operational amplifier, and the delay adjustment unit is added to the zero-crossing detector to correct the delay caused by the process and temperature. An improved common gate current mirror is used to reduce the charge injection at the output end when the current mirror is turned off. Using the improved zero-crossing detector as the comparator of the parallel analog-to-digital converter, the quantization and coding of the input signal can be completed in the sampling phase, and the residual amplification time of the MDAC in the holding phase is increased. Using the combination of misalignment error foreground correction and offset error background correction to correct the system non-ideal factor and introducing the offset error can effectively reduce the static energy in the output dynamic performance of the analog-to-digital converter. Under the simulation condition that the sampling frequency is 50m SPS and the input signal is 16.89 MHz chord wave signal, the performance of A / D conversion system is about 59 dB, the non-spurious dynamic range is about 67 dB, and the effective bit number is about 9.5 bits. The core power consumption of ADC is about 27.5 MW.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN792

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