自适应拟合负载关键路径的AVS电路的研究与设计

发布时间：2018-09-06 17:03

【摘要】：伴随着半导体产业的快速发展,芯片的集成度越来越高,由此产生的功耗问题也越来越突出。与此同时,各种便携设备飞速发展也对产品的续航能力提出了高要求。遗憾的是,电池技术却没有跟上电路技术的发展步伐,因此设计高效的电源管理方案已经迫在眉睫。自适应电压调节AVS技术采用实时的闭环电压调节方式,使得负载芯片的能耗大幅降低。本文首先分析了数字电路的功耗来源,阐述了降低负载芯片能耗的有效方法。然后介绍了当前热门的一些电源管理技术,包括动DPM策略、DVS技术以及AVS技术,并对AVS技术的突出特点进行了分析说明。在AVS技术的不同实现方式中,基于负载关键路径拟合的AVS硬件开销小、调节精度高,是一种较理想的AVS技术实现方式。随着工艺线宽减小,互连线延时变得越来越不可忽视,而传统的关键路径拟合只考虑到了逻辑门的延时,这降低了拟合的精确度。且传统的关键路径拟合方式仅仅取整个负载的关键路径,也就是延时最长的路径,这使得负载运行简单任务时,供电电压依然是按最复杂任务计算,降低了负载运行简单任务时的节能效果。本文针对这两个问题做了改进与创新,将互连线延时与逻辑门延时分开拟合,提高了拟合精度;对负载不同工作任务的关键路径分开进行拟合,提高了负载运行简单任务时的节能效果。本文设计的电路使用Buck变换器作为功率级,采用电压控制模式,PWM调制模式,工作频率为2MHz,环路采用相位超前补偿方式。Buck变换器输入电压3.3V,输出电压0.7V-1.8V可调,调压步进为25mV。数字负载为可进行十六位二输入加法、乘法、乘累加三种不同工作任务的运算器,工作频率范围在30MHz-100MHz。论文在详细阐述电路设计原理及工作方式后,对延时检测、调压算法、主控逻辑等电路中的关键模块做了介绍。最后,本文通过电路仿真验证了所设计AVS电路的可行性,当负载工作任务或工作频率改变时,Buck变换器能够实时将输出电压调节至能保证负载正常工作下的最低值。
[Abstract]:With the rapid development of semiconductor industry, chip integration is becoming more and more high, resulting in more and more prominent power problems. At the same time, the rapid development of various portable equipment also put forward high requirements for the product's endurance. Unfortunately, battery technology has not kept pace with the development of circuit technology, so it is urgent to design efficient power management scheme. Adaptive voltage regulation (AVS) technology adopts real-time closed-loop voltage regulation, which greatly reduces the energy consumption of the load chip. In this paper, the power source of digital circuit is analyzed, and the effective method of reducing load chip energy consumption is discussed. Then some popular power management technologies are introduced, including dynamic DPM strategy, DVS and AVS, and the prominent features of AVS are analyzed and explained. Among the different implementation methods of AVS, AVS based on load critical path fitting is an ideal way to realize AVS because of its low hardware overhead and high adjusting precision. With the decrease of line width, the interconnect delay becomes more and more important, but the traditional critical path fitting only considers the delay of logic gate, which reduces the precision of fitting. The traditional critical path fitting method only takes the critical path of the whole load, that is, the longest delay path, which makes the power supply voltage is still calculated according to the most complex task when the load runs simple task. Reduces the energy saving effect when the load runs the simple task. In this paper, the two problems are improved and innovated, the interconnect delay and logic gate delay are fitted separately, the fitting precision is improved, and the critical paths of different work tasks are fitted separately. The energy saving effect is improved when the load is running simple task. The circuit designed in this paper uses Buck converter as power stage, voltage control mode and PWM modulation mode, working frequency is 2MHz, loop adopts phase leading compensation mode. Buck converter uses 3.3V input voltage, output voltage 0.7V-1.8V is adjustable, voltage step is 25mV. The digital load is an arithmetic machine that can add 16-bit two input and multiply three different work tasks. The frequency range is 30MHz-100MHz. After expatiating the design principle and working mode of the circuit, the paper introduces the key modules of the circuit, such as delay detection, voltage regulation algorithm, main control logic and so on. Finally, the feasibility of the designed AVS circuit is verified by circuit simulation. When the load task or frequency is changed, the output voltage of the Buck converter can be adjusted to the lowest value under the normal operation of the load in real time.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402

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