集成电路ESD失效机理和ESD防护电路研究

发布时间：2018-09-12 11:37

【摘要】：随着集成电路的发展,芯片采用先进的工艺,性能越来越好。然而这些先进的工艺对芯片的静电放电(ESD)的承受能力削弱,同时人们对于芯片ESD的防护要求不但没有降低,反而越来越高,这使得ESD防护电路更加不容易设计。国内ESD防护的研究相对落后于国际先进水平,特别是国产的集成电路芯片,ESD已经使芯片的成品率和可靠性大大降低,因此对芯片ESD的研究意义非常重大。本文针对国产JSR26C32X-S型抗辐射四路差分接收器芯片,通过对芯片的测试和失效分析对其进行ESD评估。主要研究内容包括对JSR26C32X-S型芯片进行三种静电放电模型(HBM、MM和CDM)的测试,然后对其ESD失效机理分析,并对三种放电模型下抗ESD性能差异对比和改进设计。首先设计三种放电模型的测试方案,并测得JSR26C32X-S型芯片在人体模型(HBM)静电放电测试下的失效阈值为5000V,在机器模型(MM)静电放电测试下的失效阈值为200V,在器件充电模型(CDM)静电放电测试下的失效阈值为3000V。对三种失效进行了对比,并进行失效原因分析,发现HBM和MM模型下芯片的差分输入管脚最容易失效,失效的具体原因是连接ESD防护二极管的多晶硅互连线被击穿。为了提高该款芯片对HBM和MM静电放电的承受能力,对芯片差分输入管脚的ESD防护提出改进的保护电路(使用更高效的GGNMOS或SCR防护结构)及改进措施。从测试结果还可以发现JSR26C32X-S型芯片的CDM静电放电防护能力非常高,分析其原因,发现是输出缓冲级电路中面积非常大的NMOS和PMOS管在ESD事件发生时泄放了大量ESD电流。综上所述,本文对国产JSR26C32X-S型抗辐射四路差分接收器芯片的ESD防护进行了研究,通过一系列测试和失效分析,找出其最容易失效的地方,并提出了改进的ESD防护结构。将其应用于该芯片,甚至应用于工业和军事领域的其它同类型芯片,将大大提高芯片的成品率以及其可靠性。
[Abstract]:With the development of integrated circuit, the chip adopts advanced technology, the performance is getting better and better. However, these advanced processes weaken the ability to withstand the electrostatic discharge (ESD) of the chip, and at the same time, the protection requirements for the chip ESD are not reduced, but higher and higher, which makes the ESD protection circuit more difficult to design. The research of ESD protection in China lags behind the advanced level of the world, especially the domestic integrated circuit chip ESD has greatly reduced the yield and reliability of the chip, so the research on chip ESD is of great significance. In this paper, ESD is evaluated by testing and failure analysis of JSR26C32X-S four-way differential receiver chip. The main contents of this paper are as follows: testing three kinds of electrostatic discharge models (HBM,MM and CDM) for JSR26C32X-S chip, then analyzing the failure mechanism of ESD, and comparing and improving the difference of anti-ESD performance under the three discharge models. First, the test scheme of three discharge models is designed. The failure threshold of JSR26C32X-S chip is 5 000 V under (HBM) electrostatic discharge test of human body model, 200 V under machine model (MM) electrostatic discharge test, and 3 000 V under (CDM) electrostatic discharge test of device charging model. By comparing the three failures and analyzing the causes of the failures, it is found that the differential input pin of the chip under the HBM and MM models is the most likely to fail, and the specific reason of the failure is the breakdown of the polysilicon interconnects connected to the ESD protection diodes. In order to improve the resistance of the chip to HBM and MM electrostatic discharge, an improved protection circuit (using a more efficient GGNMOS or SCR protective structure) and improved measures are proposed for the ESD protection of the differential input pin of the chip. It can also be found from the test results that the CDM electrostatic discharge protection capability of the JSR26C32X-S chip is very high. The reason is that the NMOS and PMOS transistors with a very large area in the output buffer circuit discharge a large amount of ESD current during the ESD event. To sum up, the ESD protection of domestic JSR26C32X-S four-way differential receiver chip is studied. Through a series of tests and failure analysis, the most vulnerable areas of failure are found out, and an improved ESD protection structure is proposed. Applying it to the chip, even to other similar chips in industrial and military fields, will greatly improve the yield and reliability of the chips.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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