晶体管级与逻辑级数字集成电路软错误防护研究

发布时间：2018-11-17 08:01

【摘要】：集成电路工艺水平的发展使得特征尺寸减小、临界电荷量变低,电路很容易受到外界影响而产生故障。不论是宇宙太空中,还是我们赖以生存的大气层中,都存在着影响集成电路可靠性的辐射粒子。高能辐射粒子撞击器件的灵敏区,会使其发生电离效应,产生高密度的电子空穴对,影响电路稳定性。辐射造成的错误分为软错误和硬错误,硬错误是永久性损伤,而软错误是瞬时错误,对器件本身没有损伤,可以恢复。本文主要研究晶体管级和逻辑级的数字集成电路软错误防护方法。首先,针对几种国内外已有的晶体管和逻辑级容错技术进行探究,对各种容错电路结构进行原理分析和电路仿真,并验证其软错误防护性能。接着,本文提出了一种晶体管级的软错误防护方案——开关型冗余加固脉冲触发器,同样对它进行电路仿真与容错验证。由仿真结果可知,此触发器具有良好的容错性能,能够防护大部分关键节点发生的软错误。最后,本文采用层次化的全定制设计方法,对开关型冗余加固脉冲触发器进行投片与测试,以验证它的基本功能与软错误防护性能。本文的创新点在于提出了开关型冗余加固脉冲触发器结构。此触发器以一定的面积代价换取软错误防护性能的提高。本文首先提出了开关型脉冲触发器结构,此脉冲触发器的晶体管数目较少,并且由于是脉冲触发器,因此它的时钟负载较小。在开关型脉冲触发器的基础上,增加部分冗余电路,并结合C单元,设计出具有软错误防护功能的脉冲触发器。冗余电路的增加使得开关型冗余加固脉冲触发器晶体管数目增多,相比于标准单元,付出了一定的面积代价。本文的不足之处在于只对样片进行了基本功能测试,由于条件原因,辐照实验未能完成。但是从原理分析以及电路仿真结果来看,此触发器具有较好的软错误防护性能,能够防护大部分关键节点的软错误。开关型冗余加固脉冲触发器以部分面积代价换取良好的容错性能。相比于标准单元,它的面积增加了69%,功耗也会相应的增加。但是对于可靠性要求较高的集成电路来说,以部分面积和功耗代价来换取性能的稳定是很值得的。而且,与传统的软错误防护技术相比,该触发器所付出的面积代价较小,并且不需要浪费额外的时钟周期,可行性较强。
[Abstract]:With the development of integrated circuit technology, the characteristic size is reduced, the critical charge is reduced, and the circuit is easily affected by the outside world. Whether in space or in the atmosphere on which we live, there are radioactive particles that affect the reliability of integrated circuits. The high energy radiation particles impact the sensitive region of the device, which will cause ionization effect and produce high density electron hole pairs, which will affect the stability of the circuit. The errors caused by radiation can be divided into soft error and hard error, hard error is permanent damage, and soft error is instantaneous error, which has no damage to the device itself and can be recovered. In this paper, the methods of digital integrated circuit soft error protection at transistor level and logic level are studied. Firstly, several kinds of transistor and logic level fault-tolerant technology are studied, the principle analysis and circuit simulation of various fault-tolerant circuit structures are carried out, and the performance of soft error prevention is verified. Then, this paper presents a kind of soft error protection scheme at transistor level, which is the switch type redundant strengthened pulse trigger, which is also simulated and fault-tolerant. The simulation results show that the flip-flop has good fault-tolerant performance and can protect most key nodes from soft errors. Finally, in order to verify its basic function and soft error prevention performance, this paper adopts a hierarchical, fully customized design method to cast and test the switch redundancy reinforced pulse flip-flop. The innovation of this paper lies in the structure of switched redundancy reinforced pulse flip-flop. This flip-flop trades for the improvement of the performance of soft error protection at a certain area cost. In this paper, a switch type pulse flip-flop structure is proposed. The number of transistors in this pulse flip-flop is small, and its clock load is small because it is a pulse flip-flop. On the basis of switching pulse flip-flop, a pulse flip-flop with soft error protection is designed by adding some redundant circuits and combining with C unit. With the increase of redundant circuits, the number of switched redundancy strengthened pulse trigger transistors increases, which pays a certain area cost compared with the standard cells. The shortcoming of this paper is that the basic function of the sample has been tested only, but the irradiation experiment has not been completed because of the condition. But from the analysis of principle and the result of circuit simulation, it is shown that this trigger has better performance of soft error prevention and can protect most key nodes from soft error. Switching redundancy strengthened pulse flip-flop gains good fault-tolerant performance at partial area cost. Compared with the standard cell, its area increases 69 and the power consumption increases accordingly. However, for integrated circuits with high reliability requirements, it is worth paying for performance stability at the cost of partial area and power consumption. In addition, compared with the traditional soft error prevention technology, this trigger has less area cost, and does not need to waste additional clock cycles, so it is more feasible.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN783

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