12位时间交织流水线ADC的设计及通道失配研究
发布时间：2019-02-17 15:18
【摘要】：高性能的模数转换器越来越多的应用在国防、通信和高端家电等领域,是电子信息产业中的一项关键技术。随着电子信息领域的发展,各种通信设备的工作速度不断提高,因此对于高速模数转换器的需求日趋迫切。传统结构的ADC在保证精度的情况下,速度实现几乎达到了极限。因此,将单通道的ADC并行化是突破转换速率的限制并不牺牲精度的有效方法。多通道时间交织技术存在着固有的弊端,即通道间的增益失配、失调失配和采样时刻失配会降低系统精度,需要校正技术消除误差。本文首先基于CMOS Smic0.18μm工艺设计了一款12位50MHz的单通道流水线ADC,在输入561.523k Hz的正弦信号时,信噪失真比(SNDR)达到70.3581d B,动态无杂散范围(SFDR)为77.9108d B,有效位数(ENOB)为11.5137位。在此基础上,详细分析了双通道时间交织流水线ADC的失配产生原因,通过数学推导将失调失配、增益失配和采样时刻失配对系统精度的影响进行量化,并利用Matlab建模仿真验证三种失配在时间交织系统中产生的影响。针对误差消除,采用基于LMS-FIR及CIC内插滤波的校正算法,设计了12位100M的双通道时间交织流水线ADC系统。仿真结果表明,采样时钟100MHz,输入信号频率561.523k Hz时,经过校正后系统输出的动态无杂散范围达到75.98d B。
[Abstract]:High performance analog-to-digital converters are increasingly used in defense, communications and high-end home appliances, which is a key technology in the electronic information industry. With the development of electronic information field, the working speed of various communication equipments is increasing, so the demand of high speed A / D converter is becoming more and more urgent. Under the condition of guaranteeing precision, the speed of ADC with traditional structure has almost reached the limit. Therefore, parallelization of single channel ADC is an effective method to break through the limit of conversion rate without sacrificing precision. Multi-channel time interleaving technology has its inherent disadvantages, that is, gain mismatch between channels, mismatch between channels and mismatch at sampling time will reduce the system precision, and the correction technique is needed to eliminate the error. In this paper, we first design a 12-bit 50MHz single-channel pipeline ADC, based on CMOS Smic0.18 渭 m process. When we input the sine signal of 561.523k Hz, the signal-to-noise distortion ratio (SNDR) reaches 70.3581dB, and the dynamic non-spurious range (SFDR) is 77.9108dB. The effective digit (ENOB) is 11.5137 bits. On this basis, the causes of mismatch of two-channel time-interleaved pipeline ADC are analyzed in detail. The effects of mismatch, gain mismatch and sampling time mismatch on the system precision are quantified by mathematical derivation. The effects of three mismatches on time interleaving systems are verified by Matlab modeling and simulation. Based on LMS-FIR and CIC interpolation filtering, a 12-bit 100m dual channel time interleaved pipeline ADC system is designed for error cancellation. The simulation results show that when the sampling clock is 100MHz and the input signal frequency is 561.523k Hz, the dynamic spurious range of the output is 75.98dB after correction.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
本文编号：2425301
[Abstract]:High performance analog-to-digital converters are increasingly used in defense, communications and high-end home appliances, which is a key technology in the electronic information industry. With the development of electronic information field, the working speed of various communication equipments is increasing, so the demand of high speed A / D converter is becoming more and more urgent. Under the condition of guaranteeing precision, the speed of ADC with traditional structure has almost reached the limit. Therefore, parallelization of single channel ADC is an effective method to break through the limit of conversion rate without sacrificing precision. Multi-channel time interleaving technology has its inherent disadvantages, that is, gain mismatch between channels, mismatch between channels and mismatch at sampling time will reduce the system precision, and the correction technique is needed to eliminate the error. In this paper, we first design a 12-bit 50MHz single-channel pipeline ADC, based on CMOS Smic0.18 渭 m process. When we input the sine signal of 561.523k Hz, the signal-to-noise distortion ratio (SNDR) reaches 70.3581dB, and the dynamic non-spurious range (SFDR) is 77.9108dB. The effective digit (ENOB) is 11.5137 bits. On this basis, the causes of mismatch of two-channel time-interleaved pipeline ADC are analyzed in detail. The effects of mismatch, gain mismatch and sampling time mismatch on the system precision are quantified by mathematical derivation. The effects of three mismatches on time interleaving systems are verified by Matlab modeling and simulation. Based on LMS-FIR and CIC interpolation filtering, a 12-bit 100m dual channel time interleaved pipeline ADC system is designed for error cancellation. The simulation results show that when the sampling clock is 100MHz and the input signal frequency is 561.523k Hz, the dynamic spurious range of the output is 75.98dB after correction.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
【参考文献】
相关期刊论文 前1条
1 董庆祥;;数字校对技术在流水线ADC中的应用[J];电子器件;2005年04期
相关博士学位论文 前1条
1 叶凡;多通道时间交织模数转换器的校正与集成电路实现方法研究[D];复旦大学;2010年
相关硕士学位论文 前2条
1 罗海峰;标准数字CMOS工艺，，60M采样10bit精度流水线ADC的设计[D];上海交通大学;2011年
2 唐佳;自适应滤波算法的分析与FPGA高速实现[D];中南大学;2010年
本文编号：2425301
本文链接：https://www.wllwen.com/kejilunwen/dianzigongchenglunwen/2425301.html
