FPGA可重构计算的规模可伸缩性研究及实现
发布时间：2019-04-19 04:36
【摘要】：随着信息技术的快速发展,大数据、物联网、人工智能等热点产业所带来的信息量逐渐增大,这些产业对数据的高性能处理越来越迫切。然而,受到半导体工艺的限制,处理器的性能已难以满足应对高性能计算的需求。取而代之的是多核、众核等同构多核处理器,但是一旦同构多核处理器的计算性能达到一定极限后,则无法再随着内核数量的增加而提升。研究发现,CPU与FPGA的异构多核处理器能够满足大数据处理的计算效率,且功耗相对较低。然而尽管CPU-FPGA异构系统在高性能计算领域具有良好的优势,但其并没有得到大规模应用。主要原因有,相比于通用计算机系统,FPGA的开发效率低,并且FPGA的计算模式的规模可伸缩性差。用户在使用FPGA开发时,受到器件物理资源的限制,如果FPGA开发者不提供源代码,已开发好的应用很难部署到不同的FPGA器件上,限制了成果的大规模传播和应用。本文基于动态部分可重构技术及虚拟存储池机制,实现了FPGA可重构计算的规模可伸缩性机制,主要实现包括:将FPGA资源划分成物理资源与逻辑资源,使得用户在进行FPGA应用开发时,不再受物理资源的限制,仅需满足逻辑资源大小。为保证适应多种不同类型的应用加速,采取分等级的固定页面划分机制,页面间具有一定的兼容性,可组合调入。页面间实现了共享内存式和流水式两种通信方式。此外,为了推动FPGA大规模应用,改善其开发效率,本文提供了一套基于设计重用及解耦合思想的开发模式,鼓舞开发者分享FPGA应用成果,同时方便了用户进行应用开发,体验FPGA应用的性能加速。本文实现的FPGA可重构计算的规模可伸缩性架构在FPGA中支持SIMD/MIMD并行计算模式,并通过可重构计算单元的通信支持流水式计算模式,方便用户根据具体应用选择相应的计算模式,从而达到最大的计算效率。实验结果显示,相比较其它平台及传统FPGA应用,该架构在保持FPGA计算系统高性能、低功耗优势的同时,能有效地简化用户的编程模式,有利于推动FPGA成果的大规模传播和应用。
[Abstract]:With the rapid development of information technology, the amount of information brought by hot industries such as big data, Internet of things, artificial intelligence and so on increases gradually, and the high-performance processing of data in these industries is becoming more and more urgent. However, due to the limitations of semiconductor technology, the performance of the processor is difficult to meet the needs of high-performance computing. Instead of multi-core and multi-core isomorphic multi-core processors, once the computing performance of isomorphic multi-core processors reaches a certain limit, it can no longer be improved with the increase of the number of cores. It is found that the heterogeneous multicore processors of CPU and FPGA can satisfy the computing efficiency of big data and the power consumption is relatively low. However, although CPU-FPGA heterogeneous systems have good advantages in the field of high performance computing, they have not been applied on a large scale. The main reasons are that compared with the general computer system, the development efficiency of FPGA is low, and the scale scalability of FPGA computing mode is poor. When users use FPGA, they are limited by the physical resources of devices. If FPGA developers do not provide source code, it is difficult to deploy well-developed applications to different FPGA devices, which limits the large-scale dissemination and application of the results. Based on dynamic partial reconfigurable technology and virtual storage pool mechanism, the scale scalability mechanism of FPGA reconfigurable computing is realized in this paper. The main realization includes: dividing FPGA resources into physical resources and logical resources. When users are developing FPGA applications, they are no longer limited by physical resources, and only need to satisfy the logical resource size. In order to adapt to a variety of different types of application acceleration, a hierarchical fixed page partition mechanism is adopted, which has certain compatibility among pages and can be combined into. Pages between the realization of shared memory and flow of two types of communication mode. In addition, in order to promote the large-scale application of FPGA and improve its development efficiency, this paper provides a set of development mode based on the idea of design reuse and decoupling, which encourages developers to share the results of FPGA application, and at the same time makes it convenient for users to carry out application development. Experience performance acceleration for FPGA applications. The scale scalability architecture of FPGA reconfigurable computing implemented in this paper supports the SIMD/MIMD parallel computing pattern in FPGA, and supports the flowing water computing pattern through the communication of reconfigurable computing units. It is convenient for the user to choose the corresponding calculation mode according to the specific application, so as to achieve the maximum calculation efficiency. The experimental results show that compared with other platforms and traditional FPGA applications, this architecture not only keeps the high performance and low power consumption advantage of FPGA computing system, but also simplifies the programming mode of users effectively, and is helpful to promote the large-scale dissemination and application of FPGA achievements.
【学位授予单位】：江南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791
本文编号：2460606
[Abstract]:With the rapid development of information technology, the amount of information brought by hot industries such as big data, Internet of things, artificial intelligence and so on increases gradually, and the high-performance processing of data in these industries is becoming more and more urgent. However, due to the limitations of semiconductor technology, the performance of the processor is difficult to meet the needs of high-performance computing. Instead of multi-core and multi-core isomorphic multi-core processors, once the computing performance of isomorphic multi-core processors reaches a certain limit, it can no longer be improved with the increase of the number of cores. It is found that the heterogeneous multicore processors of CPU and FPGA can satisfy the computing efficiency of big data and the power consumption is relatively low. However, although CPU-FPGA heterogeneous systems have good advantages in the field of high performance computing, they have not been applied on a large scale. The main reasons are that compared with the general computer system, the development efficiency of FPGA is low, and the scale scalability of FPGA computing mode is poor. When users use FPGA, they are limited by the physical resources of devices. If FPGA developers do not provide source code, it is difficult to deploy well-developed applications to different FPGA devices, which limits the large-scale dissemination and application of the results. Based on dynamic partial reconfigurable technology and virtual storage pool mechanism, the scale scalability mechanism of FPGA reconfigurable computing is realized in this paper. The main realization includes: dividing FPGA resources into physical resources and logical resources. When users are developing FPGA applications, they are no longer limited by physical resources, and only need to satisfy the logical resource size. In order to adapt to a variety of different types of application acceleration, a hierarchical fixed page partition mechanism is adopted, which has certain compatibility among pages and can be combined into. Pages between the realization of shared memory and flow of two types of communication mode. In addition, in order to promote the large-scale application of FPGA and improve its development efficiency, this paper provides a set of development mode based on the idea of design reuse and decoupling, which encourages developers to share the results of FPGA application, and at the same time makes it convenient for users to carry out application development. Experience performance acceleration for FPGA applications. The scale scalability architecture of FPGA reconfigurable computing implemented in this paper supports the SIMD/MIMD parallel computing pattern in FPGA, and supports the flowing water computing pattern through the communication of reconfigurable computing units. It is convenient for the user to choose the corresponding calculation mode according to the specific application, so as to achieve the maximum calculation efficiency. The experimental results show that compared with other platforms and traditional FPGA applications, this architecture not only keeps the high performance and low power consumption advantage of FPGA computing system, but also simplifies the programming mode of users effectively, and is helpful to promote the large-scale dissemination and application of FPGA achievements.
【学位授予单位】：江南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791
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