考虑NBTI的动态休眠管尺寸电源门控设计

发布时间：2019-05-08 13:36

【摘要】：当前纳米互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)集成电路设计中,利用电源门控(power gating,PG)技术来降低静态功耗已成为一种趋势。随着集成电路工艺尺寸的不断缩小,负偏置温度不稳定性(negative bias temperature instability,NBTI)带来的电路老化问题越来越严重。当Header型PG电路处于正常工作模式时,休眠管(sleep transistor,ST)会受到NBTI老化效应的影响,导致PG电路的性能损失加重。文章通过对PG电路的NBTI老化特性分析,提出了考虑NBTI的PG电路性能损失模型;利用PG电路的NBTI老化特性将ST进行分组,并通过间断接通ST,等效于动态调节ST的尺寸或导通电阻,来减小由ST老化引起的PG电路性能损失。结果表明,动态ST尺寸方法与传统ST尺寸方法相比,可以使PG电路的使用寿命提高30%左右,并且提出的模型与HSPICE仿真结果所得到的趋势相吻合。
[Abstract]:In the current design of nano-complementary metal oxide semiconductor (complementary metal oxide semiconductor,CMOS) integrated circuits, the use of power gating (power gating,PG) technology to reduce static power consumption has become a trend. With the shrinking of IC process size, negative bias temperature instability (negative bias temperature instability,NBTI) brings about more and more serious circuit aging problems. When the head type PG circuit is in normal working mode, the dormant tube (sleep transistor,ST) will be affected by the aging effect of NBTI, and the performance loss of the PG circuit will be aggravated. Based on the analysis of the aging characteristics of NBTI in PG circuits, a performance loss model of PG circuits considering NBTI is proposed in this paper. The NBTI aging characteristics of the PG circuit are used to group the ST and to reduce the performance loss of the PG circuit caused by the ST aging by adjusting the size or on-resistance of the ST dynamically by intermittently switching on the ST,. The results show that the dynamic ST size method can increase the service life of PG circuits by about 30% compared with the traditional ST size method, and the proposed model is consistent with the trend of HSPICE simulation results.
【作者单位】：合肥工业大学电子科学与应用物理学院;安徽理工大学计算机科学与工程学院;
【基金】：国家自然科学基金资助项目(61371025;61574052;61404001)
【分类号】：TN432

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