纳米工艺下集成电路的容软错误锁存器设计
发布时间：2019-05-17 13:54
【摘要】：集成电路产业是信息技术产业的基础和核心,也是国家关注的战略性产业。随着半导体技术的飞跃式进步,集成电路的性能在不断提高的同时,所面临的可靠性问题也越来受到人们的关注。随着半导体工艺的飞速发展,集成电路的特征尺寸已进入纳米时代,供电电压和敏感节点能储存的电荷也随之减小,CMOS电路受到辐射影响更容易发生软错误。本文针对纳米工艺下集成电路的软错误问题,在研究现有加固锁存器设计的基础上,提出有效的加固锁存器设计方案,本文主要工作如下:本文提出了能够容忍单粒子单节点翻转的STSRL锁存器。该锁存器采用了1P-2N单元、输入分离的钟控反相器以及C单元,使得本锁存器对单粒子翻转能够实现自恢复,并且可以用于时钟门控电路。STSRL锁存器通过采用高速通路设计用以减小延迟,采用钟控设计用以降低功耗。该锁存器不仅能够容忍单粒子单节点翻转,还能够自恢复,具有良好的加固能力。同时相比于已有的加固锁存器其开销大幅降低。HSPICE仿真结果表明,相比于HLR-CG1、HLR-CG2、TMR、HiPeR-CG锁存器,STSRL锁存器的功耗平均下降了 44.40%,延迟平均下降了 81%,PDP平均下降了 94.20%,面积开销平均减少了 1.80%。本文提出了能够容忍单粒子双节点翻转的SEDNUTL锁存器,该锁存器采用了双模冗余容错技术,它能够同时容忍单粒子单节点翻转和单粒子双节点翻转。与同类型能容忍 DNU 的 DOUNT、DeltaDICE、DNCS、HRDUNT、NTHLTCH 加固锁存器设计相比,SEDNUTL锁存器的延迟平均下降了 90.66%,功耗平均增加了 14.74%,PDP平均下降了 90.27%,面积平均减少了 16.22%;而且在供电电压、工作温度和阈值电压波动时,该锁存器的延迟对其变化不敏感。
[Abstract]:Integrated circuit industry is the foundation and core of information technology industry, and it is also the strategic industry concerned by the state. With the rapid progress of semiconductor technology, the performance of integrated circuits is improving, and the reliability problems faced by integrated circuits have attracted more and more attention. With the rapid development of semiconductor technology, the characteristic size of integrated circuits has entered the nanometer era, and the power supply voltage and the charge stored by sensitive nodes are also reduced. CMOS circuits are more prone to soft errors affected by radiation. In order to solve the soft error problem of integrated circuits in nanotechnology, based on the study of the existing reinforcement latch design, an effective reinforcement latch design scheme is proposed in this paper. The main work of this paper is as follows: in this paper, a STSRL latch which can tolerate single particle single node flip is proposed. The latch adopts a 1P-2N unit, an input separated clock-controlled inverter and a C unit, so that the latch can realize self-recovery for a single particle flip. STSRL latch is designed to reduce delay by using high speed path design and clock control design to reduce power consumption. The latch can not only tolerate single particle single node flip, but also self-recovery, and has good reinforcement ability. At the same time, compared with the existing strengthened latch, the cost of STSRL latch is greatly reduced. HSPice simulation results show that compared with HLR-CG1,HLR-CG2,TMR,HiPeR-CG latch, the power consumption of STSRL latch is reduced by 44.40% on average, and the delay is reduced by 81% on average. On average, PDP decreased by 94.20%, and area cost decreased by 1.80%. In this paper, a SEDNUTL latch is proposed, which can tolerate single particle double node flip. The latch adopts dual mode redundant fault tolerant technique, which can tolerate single particle single node flip and single particle double node flip at the same time. Compared with the same type of DOUNT,DeltaDICE,DNCS,HRDUNT,NTHLTCH reinforcement latch design which can tolerate DNU, the delay of SEDNUTL latch is reduced by 92.66%, the power consumption is increased by 14.74%, and the PDP is reduced by 9027%. The area decreased by 16.22% on average. Moreover, when the supply voltage, operating temperature and threshold voltage fluctuate, the delay of the latch is not sensitive to its change.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402
本文编号：2479143
[Abstract]:Integrated circuit industry is the foundation and core of information technology industry, and it is also the strategic industry concerned by the state. With the rapid progress of semiconductor technology, the performance of integrated circuits is improving, and the reliability problems faced by integrated circuits have attracted more and more attention. With the rapid development of semiconductor technology, the characteristic size of integrated circuits has entered the nanometer era, and the power supply voltage and the charge stored by sensitive nodes are also reduced. CMOS circuits are more prone to soft errors affected by radiation. In order to solve the soft error problem of integrated circuits in nanotechnology, based on the study of the existing reinforcement latch design, an effective reinforcement latch design scheme is proposed in this paper. The main work of this paper is as follows: in this paper, a STSRL latch which can tolerate single particle single node flip is proposed. The latch adopts a 1P-2N unit, an input separated clock-controlled inverter and a C unit, so that the latch can realize self-recovery for a single particle flip. STSRL latch is designed to reduce delay by using high speed path design and clock control design to reduce power consumption. The latch can not only tolerate single particle single node flip, but also self-recovery, and has good reinforcement ability. At the same time, compared with the existing strengthened latch, the cost of STSRL latch is greatly reduced. HSPice simulation results show that compared with HLR-CG1,HLR-CG2,TMR,HiPeR-CG latch, the power consumption of STSRL latch is reduced by 44.40% on average, and the delay is reduced by 81% on average. On average, PDP decreased by 94.20%, and area cost decreased by 1.80%. In this paper, a SEDNUTL latch is proposed, which can tolerate single particle double node flip. The latch adopts dual mode redundant fault tolerant technique, which can tolerate single particle single node flip and single particle double node flip at the same time. Compared with the same type of DOUNT,DeltaDICE,DNCS,HRDUNT,NTHLTCH reinforcement latch design which can tolerate DNU, the delay of SEDNUTL latch is reduced by 92.66%, the power consumption is increased by 14.74%, and the PDP is reduced by 9027%. The area decreased by 16.22% on average. Moreover, when the supply voltage, operating temperature and threshold voltage fluctuate, the delay of the latch is not sensitive to its change.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402
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