PCIe总线物理层弹性缓冲设计与实现

发布时间：2017-12-27 05:02

本文关键词：PCIe总线物理层弹性缓冲设计与实现　出处：《计算机技术与发展》2016年06期 　论文类型：期刊论文

【摘要】：PCIe是在PCI总线的基础上提出的新一代总线和接口标准,它原来的名称为"3GIO",是由英特尔在2001年提出的。PCIe属于高速串行点对点双通道高带宽传输,所连接的设备分配独享通道带宽,不共享总线带宽,主要支持主动电源管理、错误报告、端对端的可靠性传输、热插拔以及服务质量(QOS)等功能。PCIe作为高速串行数据总线以其众多的优点在计算机、通讯、航空航天等领域得到了广泛应用。为了实现稳定可靠的数据通讯,必须解决总线恢复时钟域数据和本地时钟域数据的同步问题,弹性缓冲区是实现PCIe总线接口数据同步机制的有效方法。文中根据PCIe协议要求,分析PCIe总线通信中时钟偏差的多种场景,设计了一款采用20位数据总线,读写时钟频率可达250 MHz的弹性缓冲,有效解决了PCIe总线通信中总线恢复时钟域与本地时钟域的数据同步问题。
[Abstract]:PCIe is a new generation of bus and interface standards based on the PCI bus. Its original name is "3GIO", which was proposed by Intel in 2001. PCIe is a high-speed serial point-to-point dual channel high bandwidth transmission. The connected device distribus exclusive channel bandwidth and does not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliability transmission, hot swap and QOS. As a high-speed serial data bus, PCIe has been widely used in many fields, such as computer, communication, aerospace and other fields. In order to achieve stable and reliable data communication, we must solve the problem of synchronization between clock domain data and local clock domain data during bus recovery. Elastic buffer is an effective way to achieve PCIe bus interface data synchronization mechanism. According to the requirement of PCIe protocol, analysis of various scene clock deviation PCIe bus, designed using a 20 bit data bus, read and write elastic buffer clock frequency of 250 MHz, an effective solution to the PCIe bus communication bus recovery clock domain and local clock domain data synchronization.
【作者单位】：西安航空计算技术研究所集成电路与微系统设计航空科技重点实验室;
【基金】：中国航空工业集团公司创新基金(2010BD63111)
【分类号】：TP336;TP334.7
【正文快照】： 0引言PCIe(PCI Express)是从PCI发展而来的一种系统互联接口标准。PCI和PCI-X都是基于32位以及64位的并行总线,而PCIe则使用高速串行总线。PCIe后向兼容于PCI,能够灵活地提供大峰值带宽。PCIe链路由多条通路组成,在链路中增加更多的通路可提高PCIe链路的带宽。规范支持的链路

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