基于PowerPCAltiVec模拟器的研究与实现

发布时间：2018-01-03 00:25

本文关键词：基于PowerPCAltiVec模拟器的研究与实现　出处：《广西工学院》2012年硕士论文　论文类型：学位论文

【摘要】：在嵌入式系统设计中，工程师们通常采用模型驱动工程（MDE）的方法来建立软、硬件高层次模型。而快速虚拟原型平台正是可以在高层次抽象下模拟系统的工具软件，而不仅仅是泛函算法仿真。快速虚拟原型平台可在形式化描述中得到精细化的模拟器模型，而且可运行并测试完整的嵌入式应用软件。快速虚拟原型平台已经成为了嵌入式片上系统软、硬件协同设计的关键所在。嵌入式系统随着硬件性能的增强而不断发展，而现有虚拟原型中的单一模拟器在模拟功能及效率上不能够满足软、硬件协同开发的需求。因此在嵌入式软件系统领域研究新的模拟及模拟优化技术，在快速虚拟原型架构下开发高效高可信的模拟器有着重要的意义。过去十几年以来，科研人员主要针对虚拟原型中32位及64位嵌入式处理器的模拟器展开了大量研究，而很少关注128位协处理器模拟器。事实上，协处理器的性能直接决定了嵌入式系统在某些应用方面的性能，，如多媒体、矢量绘图、通信等应用。随着128位协处理器多媒体应用等的继续增长，会给处理器虚拟原型研究领域带来更多的挑战。近似定时模拟技术（AT）、编译器优化技术（LLVM）、可变长度指令编码技术（VLE）等都是该领域存在的难题。因此本研究以挑战嵌入式系统设计和仿真的新方法为切入点，结合先进的系统建模和系统验证技术，在SimSoC虚拟原型的基础上研究了基于PowerPCAltiVec128位指令集的近似定时模拟技术、底层虚拟机（LLVM）动态编译优化技术和基于PowerPC模拟器的VLE可变长度指令编码技术以及模拟器仿真和验证技术，最终实现了高效高可信的基于SimSoC快速虚拟原型平台的PowerPCAltiVec嵌入式片上系统模拟器。本论文的主要工作有：第一，提出了构建PowerPC AltiVec128位嵌入式协处理器技术的GCC交叉编译器工具链的新方法。该工具链具有可移植性高、编译速度快、完整支持PowerPCAltiVec指令集及内建AltiVec系统函数等特点。第二，为了研究分析虚拟原型的计算和译码效率，分别采用了解释型编译、动态编译、细化动态编译技术来设计和实现PowerPC AltiVec指令集模拟器。研究了先进的用于优化模拟器执行效率的基于底层虚拟机（LLVM）动态编译技术。将可变长度指令编码技术应用于PowerPC AltiVec128位指令集模拟器，为其提供更好的编码密度，提高单位存储芯片空间的利用率。第三，在仿真实验中比较了在不同编译模式下PowerPC AltiVec指令集模拟器执行应用程序的效率和可信度。最后，通过单元测试、集成测试和系统测试对PowerPC AltiVec指令集模拟器进行完整的跟踪及测试以达到其可验证性。
[Abstract]:In embedded system design, engineers usually use model-driven engineering (MDE) to build software. The hardware high-level model. And the rapid virtual prototype platform is the tool software which can simulate the system under the high-level abstraction. It is not just functional algorithm simulation. The rapid virtual prototype platform can obtain a refined simulator model in formal description. The rapid virtual prototyping platform has become the key of the software and hardware collaborative design of embedded system. With the development of hardware performance, the single simulator in the existing virtual prototype can not meet the simulation function and efficiency. Therefore, new simulation and simulation optimization techniques are studied in the field of embedded software system. It is of great significance to develop an efficient and trusted simulator in the framework of rapid virtual prototyping. Over the past more than ten years. Researchers mainly focus on the virtual prototype of 32-bit and 64-bit embedded processor emulators, but pay little attention to 128-bit coprocessor emulators. The performance of coprocessor directly determines the performance of embedded system in some applications, such as multimedia, vector drawing, communication and so on. It will bring more challenges to the field of processor virtual prototyping. Approximate timing simulation technology, compiler optimization technology LLVM). Variable length instruction coding (VLEE) is a difficult problem in this field. Therefore, this research focuses on the challenge of new methods of embedded system design and simulation. Combined with advanced system modeling and system verification technology, the approximate timing simulation technology based on PowerPCAltiVec128 bit instruction set is studied on the basis of SimSoC virtual prototype. The dynamic compilation and optimization technology of the underlying virtual machine, the VLE variable length instruction coding technology based on PowerPC simulator, and the simulator simulation and verification technology. Finally, an efficient and trusted PowerPCAltiVec embedded system simulator based on SimSoC rapid virtual prototype platform is implemented. The main work of this paper is as follows: first. A new method of constructing GCC cross-compiler toolchain based on PowerPC AltiVec128 bit embedded coprocessor technology is presented, which has high portability and high compilation speed. Fully support the PowerPCAltiVec instruction set and built-in AltiVec system functions. Second, in order to study the virtual prototype of computing and decoding efficiency. Interpretive compilation and dynamic compilation are used respectively. Design and implementation of PowerPC AltiVec instruction set simulator based on dynamic compilation technology. Dynamic compiling technique. The variable length instruction coding technique is applied to PowerPC AltiVec128 bit instruction set simulator. To provide a better coding density, improve the utilization of unit memory chip space. Third. In the simulation experiment, the efficiency and reliability of the PowerPC AltiVec instruction set simulator to execute the application program in different compilation modes are compared. Finally, the unit test is passed. PowerPC AltiVec instruction set simulator is tracked and tested by integrated test and system test to achieve its verifiability.
【学位授予单位】：广西工学院
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP368.1

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