基于基地址寄存器映射的数据高速缓存设计研究

发布时间：2018-01-03 03:01

本文关键词：基于基地址寄存器映射的数据高速缓存设计研究　出处：《浙江大学》2013年硕士论文　论文类型：学位论文

【摘要】：高速缓存作为内存与处理器之间的桥梁,其性能与功耗问题日益受到关注。本文围绕高速缓存的低功耗技术,研究了存储器访问特性和零级数据高速缓存相关技术,为本文设计提供理论依据。本文的主要内容及创新点包括： 1.提出一种适用于嵌入式处理器的基于基地址寄存器映射的数据缓存访问方法。该方法的核心思想是在加载指令执行过程中动态构建基地址寄存器与目标数据的局部性访问历史,并通过设计基地址寄存器跟踪缓存器在指令译码后直接获得目标数据,从而加速加载指令的数据获取过程,减少地址计算和对高速缓存的访问。测试基准的运行结果显示,基于本方法的处理器性能提高平均约3.7%,数据高速缓存功耗降低平均约16.6%。 2.提出一种既能降低高速缓存访问功耗,又能提升处理器性能的零级数据高速缓存结构。该结构基于基地址寄存器映射,利用索引跟踪技术,通过在译码级加入索引跟踪器,在装载/存储单元加入地址检查表,来达到减少装载指令访问延时与降低访问功耗的目的。测试基准的运行结果显示,基于基地址寄存器映射的零级数据高速缓存能使数据高速缓存功耗降低平均约28%,处理器性能提升平均约3.5%,与常规零级数据高速缓存相比,处理器性能提升平均约7.4%,功耗降低作用相同。
[Abstract]:Cache, as a bridge between memory and processor, has attracted more and more attention on its performance and power consumption. This paper focuses on the low-power technology of cache. The memory access characteristics and zero-level data cache technologies are studied, which provide a theoretical basis for the design of this paper. The main contents and innovations of this paper are as follows: 1. A data cache access method based on base address register mapping is proposed for embedded processor. The key idea of this method is to dynamically construct the base address register and the target number during the execution of the instruction. According to the local visit history. By designing the base address register tracking buffer, the target data can be obtained directly after the instruction decoding, thus speeding up the data acquisition process of the loading instruction. The test results show that the performance of the processor based on this method is improved by about 3.7 on average, and the power consumption of data cache is reduced by about 16.6. 2. A zero-level data cache architecture, which can reduce cache access power consumption and improve processor performance, is proposed, which is based on base address register mapping and uses index tracking technology. By adding an index tracker at the decoding level and adding an address check table to the load / memory unit, the purpose of reducing the load instruction access delay and the access power consumption is achieved. The running results of the test benchmark are shown. The zero-level data cache based on base address register mapping can reduce the average power consumption of the data cache by about 28%, and improve the processor performance by an average of about 3.5%, compared with the conventional zero level data cache. The average processor performance improvement is about 7.4, and the power reduction function is the same.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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