铁电薄膜制备及新型铁电存储器研究

发布时间：2018-01-03 15:02

本文关键词：铁电薄膜制备及新型铁电存储器研究　出处：《复旦大学》2013年博士论文　论文类型：学位论文

【摘要】：铁电存储器是一种利用铁电薄膜材料的自发极化在电场中两种不同取向作为逻辑单元来存储数据的非易失性存储器,且具有高速度读写、高密度集成、抗辐射等优点。本博士论文主要分为两大部分：一部分以锆钛酸铅(PZT)铁电薄膜制备方法和性能研究为基础,采用新的电学测试方法研究铁电薄膜界面钝化层效应和界面层电学特性,在其基础上研究铁电栅介质／掺铝氧化锌薄膜的晶体管存储器件；另一部分以铁酸铋(BFO)铁电薄膜制备方法和性能研究为基础,研究BFO铁电畴反转调制二极管p-n结电流的阻变存储器件。第一部分,首先利用溶胶-凝胶法(Sol-Gel)制备了锆钛酸铅(PZT)铁电薄膜,并通过微电子工艺制作了金属/铁电薄膜/金属(MFM)电容器结构以及铁电栅介质/掺铝氧化锌薄膜晶体管结构,同时对PZT铁电薄膜性能、铁电薄膜界面钝化层以及铁电栅介质／掺铝氧化锌薄膜晶体管的相关电学特性等进行分析,具体内容如下： (1)利用溶胶-凝胶法(Sol-Gel),在Pt/Ti/SiO2/Si衬底上制备PZT铁电薄膜。研究不同铅过量先体溶液对PZT薄膜铁电性能影响,并得到薄膜沉积过程中优化合理的铅含量。研究表明,在(111)晶向Pt衬底电极上制备的PZT铁电薄膜展示了良好的(111)择优取向。30%铅过量的PZT铁电薄膜足够补偿薄膜制备工艺中引发的铅损失。薄膜展示了对称且矩形的电滞回线(P-V)、良好的疲劳特性、蝴蝶状C-V曲线和良好的绝缘特性等。 (2)研究了PZT铁电薄膜矫顽电压与频率的关系,实验结果证明它符合Ishibashi的幂定律关系,频率系数βf与界面钝化层有紧密关系。PZT铁电薄膜界面钝化层会增大电畴矫顽电压,并且界面钝化层对矫顽电压依赖频率变化关系有钝化作用。这与多数科学家们认为界面层的存在会导致矫顽电压减小的观点正好相反,为电畴反转动力学的研究提供更加正确的实验数据。 (3)采用畴壁共钉扎与退钉扎效应共存的极化疲劳模型模拟了薄膜的疲劳特性。发现温度升高会恶化疲劳特性,这表明高温有利于电荷载流子移动并从电极注入到薄膜内部,而载流子注入所产生的电荷屏蔽效应阻止了新畴成核生长,从而加强铁电畴壁钉扎效应。从以上疲劳模型获得钉扎系数F1和F2与薄膜界面层导电成比例关系,证明了铁电薄膜界面钝化层导电机制符合Schottky热电荷发射机制。通得这一关系,计算出对应F1和F2处的界面钝化层的介电常数和厚度的参数值(β1)约为5320和8480,β1值随疲劳次数的增加而增大表明了铁电疲劳效应增厚了铁电薄膜界面层。该方法提供了一种研究铁电薄膜界面层介电常数、势垒高度等电学物理性质新途径。 (4)PZT铁电薄膜电容-电压(C-V)特性展现出一个漂亮的蝴蝶状(butterfly profile)图,从中得到的矫顽电压与从电滞回线中得到的矫顽电压一致。漏电流测试证明,30%铅过量的PZT铁电薄膜具有优良的绝缘特性。 (5)通过全新的脉冲电压法,从电畴反转电流中直接得到铁电薄膜矫顽电压,证实性能优良的30%铅过量的PZT铁电薄膜中界面钝化层的存在,最终得到不同电畴极化反转电流下的界面钝化层的电流-电压(Ii-Vi)关系和铁电薄膜本征矫顽电压。从以上关系中证明界面钝化层电流-电压(Ii-Vi)关系满足Schottky热电荷发射机制,进一步计算出界面钝化层的介电常数和厚度的参数值(系数βs)为14。这是传统的测量技术所无法达到的。实验表明,电畴极化反转电流与铁电薄膜本征矫顽电场(Isw-Ec)的关系满足Merz定律,并得到本征电畴壁激活场强(δ=1.4kV/cm)；纠正过去的畴壁激活场强计算中忽略了界面钝化层的影响,从而不能准确地反应本征电畴壁运动规律。 (6)采用磁控溅射法(PVD),在室温下在SiO2/Si衬底上制备出掺铝氧化锌薄膜(AZO),得到单一ZnO(002)晶相；证明在N2气氛中以及400℃退火条件下,AZO薄膜具有良好的半导体特性。成功地在Pt/Ti/SiO2/Si衬底上制备出倒栅结构的铁电栅介质/掺铝氧化锌薄膜晶体管(FeFET),在PZT铁电薄膜基础上生长出的AZO薄膜也具有择优(002)取向。铁电栅介质/掺铝氧化锌薄膜晶体管(FeFET)随着电畴正反两种不同取向能够实现开关态电流转变,栅电压VGs=0时,源漏电压VDS=1.8V时,开关比可达到1000。论文第二部分,利用脉冲激光沉积法(PLD)制备出钌酸锶(SRO)下电极导电薄膜、铁酸铋(BFO)铁电薄膜,最终采用微电子工艺技术制作出Au/BFO/SRO/STO电容器结构,实现铁电畴反转调制二极管电流的阻变存储器件,同时对BFO铁电薄膜中铁电畴反转所引起地二极管阻变性能及其导电机制等进行研究分析,具体内容如下：利用脉冲激光沉积法(PLD),成功地在不同晶向的钛酸锶(STO)单晶衬底上制备出优良导电性能的钌酸锶(SRO)下电极,(100)和(111)取向的下电极的电阻率分别为359.7μΩ·cm和367.5μΩ·cm;并且薄膜表面十分平整,粗糙度都在1nm内,均方根粗糙度(RMS)都在0.25nm内。 (1)利用PLD技术成功地在不同取向钛酸锶(STO)单晶衬底上生长出表面平整的BFO铁电薄膜。研究发现：在一定氧气压下,制备出表面平整的BFO铁电薄膜应该选择合理的沉积温度；在不同的制备氧气压下,制备出同样平整度的薄膜在较高氧气压下需要较高的沉积温度或较低的氧气压下需要较低沉积温度。以上薄膜生长规律同样也适用于在不同取向SRO/STO导电衬底上薄膜生长。物相分析表明,不管是在STO还是在SRO/STO衬底上生长出的BFO铁电薄膜都随衬底晶向择优取向生长。 (2)对BFO铁电薄膜电畴进行电学测试分析,发现厚的(100nm以上)BFO(100)铁电薄膜容易释放与衬底晶格失配引起的匹配应力,电畴钉扎现象不明显；而超薄BFO(100)铁电薄膜(几十个纳米)由晶格匹配应力效应所导致电畴钉扎现象明显。 (3)在(111)晶向STO单晶衬底上成功地制作了Au/BFO/SRO/STO电容器结构,具有随铁电畴反转调制二极管电流的阻变特性,可运用在非挥发的信息存储。清晰地观察到BFO铁电薄膜中二极管p-n结极性随电畴取向发生变化的现象,获得稳定的二极管电流密度可达550mA/cm2,且测量结果重复性好。通过二极管电流保持特性测试,关态电流随时间在104秒范围内基本保持恒定,开态电流稍微减小,且开关电流比一直保持在5：1。该铁电二极管阻变存储器较一般金属氧化物阻变存储器(RRAM)中电导丝产生和破灭的运行机制可靠性更高。 (4)研究表明BFO铁电二极管电流导电机制为空间电荷限制电流(SCLC)。得出BFO铁电畴反转所引起二极管极性改变现象是由界面控制的类体效应导电机制,其物理特性是通过极化反转控制界面陷阱密度梯度分布实现正向和反向二极管极性改变。
[Abstract]:Ferroelectric memory is a non-volatile memory using a ferroelectric thin films of spontaneous polarization in the electric field of two different orientation as a logical unit to store data, and has the advantages of high speed of reading and writing, high density integration, has the advantages of anti radiation and so on. This thesis is mainly divided into two parts: one part is to zirconium titanate lead (PZT) ferroelectric thin film preparation method and performance research as the foundation, the new electrical test method of ferroelectric thin film interface passivation layer effect and interface layer using electrical properties, ferroelectric gate dielectric / aluminum doped Zinc Oxide film based on the transistor storage device; the other part of the BiFeO3 ferroelectric (BFO) film preparation method and Performance Research Based on BFO ferroelectric domain inversion MODULATION DIODE p-n junction current resistive memory devices.
The first part, firstly using sol gel method (Sol-Gel) preparation of lead zirconate titanate (PZT) ferroelectric thin films, and made of metal / metal / ferroelectric thin films by microelectronic technology (MFM) capacitor structure and ferroelectric gate dielectric / Al doped thin film transistor structure of Zinc Oxide, while PZT ferroelectric thin films properties, interface analysis the passivation layer of ferroelectric thin films and ferroelectric gate dielectric / Al doped thin film transistor of the Zinc Oxide electric characteristic, the specific contents are as follows:
(1) using sol gel method (Sol-Gel), the preparation of PZT ferroelectric thin films on Pt/Ti/SiO2/Si substrates. The influence of different lead in excess of the precursor solution on the ferroelectric properties of PZT thin films, and the lead content optimization during film deposition. The results show that the (111) crystal to Pt substrate electrode for PZT ferroelectric the films show good (111) preferred orientation of PZT ferroelectric thin films.30% lead excessive lead loss caused in the process of preparing thin films. The film shows enough compensation electric hysteresis loop and rectangular symmetry (P-V), good fatigue properties, butterfly shaped C-V curve and good insulation properties.
(2) to study the relationship of PZT ferroelectric thin films of coercive voltage and frequency. The experimental results show that it meets the power law relationship between Ishibashi, F and beta frequency coefficient of interface passivation layer of.PZT ferroelectric thin films are closely related to the interface passivation layer increases domain coercive voltage, and the interface passivation layer of the coercive voltage dependent frequency variation a passivation. Which most scientists think that the interfacial layer will lead to the decrease of the coercive voltage was opposite, provide experimental data for more accurate research for domain switching dynamics.
(3) the total domain wall pinning and depinning polarization fatigue model the effect of the coexistence of fatigue properties of thin films was simulated. The temperature will find deterioration of fatigue properties, which indicates that the high temperature is in favor of mobile charge carriers and injected from the electrode into the film, while the carrier injection charge shielding effect caused by the stop into a new domain nuclear growth, thereby strengthening the ferroelectric domain wall pinning effect. The pinning coefficient F1 and the interface of F2 and the thin film layer of conductive proportion from the above fatigue model, proved that the ferroelectric thin film interface passivation layer of conductive mechanism with Schottky thermal charge emission mechanism. Through this relationship, calculate the parameters of the interface passivation layer corresponding to F1 and F2 the dielectric constant and the thickness of the value (beta 1) is about 5320 and 8480, beta 1 increased with the increasing number of fatigue showed thickening of the ferroelectric fatigue effect of ferroelectric thin film interface layer. The method provides a kind of Research A new approach to the electrical and physical properties of the interface layer of ferroelectric thin films, such as the dielectric constant and the barrier height, is investigated.
(4) PZT ferroelectric thin film capacitance voltage (C-V) characteristics show a beautiful butterfly (Butterfly profile), the coercive voltage gain consistent with that obtained from the hysteresis loop of the coercive voltage. The leakage current test, PZT ferroelectric thin films with excess Pb 30% excellent insulating properties.
(5) the new pulse voltage method, get the ferroelectric thin film of coercive voltage directly from the domain switching current, confirmed the excellent performance of the interface passivation layer 30% Pb excess PZT ferroelectric thin films in the presence of final current voltage interface passivation layer of different electric poled under the current (Ii-Vi) of the intrinsic coercive voltage relationship and ferroelectric thin films. The interface passivation current voltage from the above relationship (Ii-Vi) between the Schottky meet the thermal charge emission mechanism, further calculates the parameters of interfacial passivation layer thickness and dielectric constant value (beta s) 14. which is unable to achieve the traditional measurement technique. Experimental results show that the intrinsic coercive electric field poled ferroelectric thin films (Isw-Ec) and the current relationship to meet Merz's law, and the intrinsic electric field activation domain wall (delta =1.4kV/cm); correct domain wall past activation calculation ignores the intensity of interfacial blunt The influence of the chemical layer can not accurately reflect the law of the intrinsic domain wall motion.
(6) by magnetron sputtering (PVD), at room temperature were fabricated on SiO2/Si substrate aluminum doped thin film (AZO), Zinc Oxide ZnO (002) single crystal phase; that in N2 atmosphere and annealed at 400 C conditions, AZO thin films have good semiconductor properties. The successful preparation of ferroelectric gate medium / inverted gate structure of Al doped Pt/Ti/ thin film transistor in Zinc Oxide SiO2/Si substrate (FeFET), AZO films grown in PZT ferroelectric thin films on the basis of a preferred (002) orientation. The ferroelectric gate dielectric / Al doped thin film transistor (FeFET) with the Zinc Oxide domain and two different orientations can realize the switch state current, the gate voltage VGs=0 when the source drain voltage VDS=1.8V, switch ratio can reach 1000.
The second part of the paper, using pulsed laser deposition (PLD) was prepared by acid strontium ruthenium (SRO) electrode conductive film, bismuth ferrite (BFO) ferroelectric thin films, eventually with micro electronics technology to produce Au/BFO/SRO/STO capacitor structure, realize ferroelectric domain inversion modulation of diode current resistive memory devices, at the same time for BFO ferroelectric thin film ferroelectric domain inversion caused by diode resistive properties and conducting mechanisms are analyzed, the specific contents are as follows: using pulsed laser deposition (PLD), successfully in different orientations of SrTiO3 (STO) substrates prepared strontium ruthenate with excellent electrical conductivity (SRO) electrode, (100) and (111) orientation of the lower electrode resistivity were 359.7. Cm and 367.5. Cm; and the film surface is very smooth, the roughness is within 1nm, the root mean square roughness (RMS) in 0.25nM.
(1) the use of PLD technology successfully in different orientation of SrTiO3 (STO) single crystal substrates of BFO ferroelectric thin films with smooth surface. The study found that: in a certain oxygen pressure, prepared by the deposition temperature of BFO ferroelectric thin films with smooth surface should be reasonable; the oxygen pressure of different preparation, preparation the deposition temperature also needs higher smoothness at higher oxygen pressure or lower oxygen pressure to lower deposition temperature. These thin film growth rule also applies to the film in different orientation of SRO/STO conductive substrates. Phase analysis shows that, whether in STO or BFO ferroelectric thin films on SRO/STO substrates the growth of the crystal orientation with the substrate orientation.
(2) electrical testing analysis on domain BFO ferroelectric thin film, found thick (above 100nm) BFO (100) ferroelectric thin film and substrate, should be easy to release stress caused by the lattice mismatch, domain pinning phenomenon is not obvious; and (100) BFO ultra-thin ferroelectric thin film (10 nm) stress effect the resulting domain pinning phenomenon was matched by the lattice.
(3) in the (111) crystal to STO single crystal substrate successfully produced Au/BFO/SRO/STO capacitor structure with variable characteristics with ferroelectric domain inversion modulation diode current resistance, which can be used in the information of non volatile storage. Clearly observed diode p-n junction polarity with domain orientation change of the phenomenon of BFO ferroelectric thin films in the stable diode current density up to 550mA/cm2, and the measurement results are reproducible. Keep the characteristic test through the diode current, off current with time in 104 seconds remained constant, open state current decreases slightly, and the on-off current ratio has been keeping memory than the general metal oxide resistive memory in the 5:1. ferroelectric diode resistor (RRAM) conductance in wire formation and operation mechanism of the bursting of the higher reliability.
(4) study showed that the BFO ferroelectric diode current conductive mechanism is the space charge limited current (SCLC). The BFO ferroelectric domain inversion caused by diode polarity change phenomenon is caused by the interface control class body effect conduction mechanism, its physical properties is the interface trap density gradient distribution to achieve forward and reverse the polarity of the diode changed by polarization switching control.

【学位授予单位】：复旦大学
【学位级别】：博士
【学位授予年份】：2013
【分类号】：O484;TP333

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