基于FPGA的高斯随机数发生器的设计与实现

发布时间：2018-01-03 20:05

本文关键词：基于FPGA的高斯随机数发生器的设计与实现　出处：《华南理工大学》2013年硕士论文　论文类型：学位论文

【摘要】：高斯随机数在通信和雷达系统、航空航天、脉冲测距、蒙特卡罗模拟硬件加速器等领域获得了广泛应用。现有硬件实现的高斯随机数发生器存在结构复杂、设计周期长等不足，本文对Ziggurat高斯随机数发生器和定点乘法器进行改进，以减少硬件资源，提高工作频率。完成的研究工作具体如下：第一，本文提出的嵌套分割高斯随机数发生器将高斯分布概率密度函数分为顶部、中部、尾部三个子区域，并分别进行分层嵌套分割，有效提高了对概率密度函数的近似精度，输出随机数最大值从4.3提高到8.7。分割后以正比于矩形面积的概率随机选择一个矩形区域，生成概率密度函数为对应矩形的随机数点，其横坐标即为输出的高斯随机数。在此基础上完成了改进后随机数发生器整体架构、均匀分布随机数发生器模块、尾部区域模块、顶部区域模块等关键电路的设计和仿真。第二，乘法器作为嵌套分割随机数发生器中重要模块，对随机数发生器性能有着重要影响。本文基于Radix-16冗余Booth编码，将奇数倍部分积改用冗余差分形式表示，改进后需要计算的奇数倍被乘数从1个减少到0个。将改进结构推广到Radix-32和Radix-64乘法器，奇数倍被乘数个数从3个和7个分别减少到1个，简化了控制信号产生电路和Booth解码电路，减少了硬件资源使用和延时。第三，本文对传统部分积修正方法改进，将修正位与部分积进行压缩，可将部分积数量从5个减少为4个。改进后部分积低7位到达二进制转换电路时间更早，简化了二进制转换电路结构，降低了乘法器延时和面积。TSMC180nm工艺下Design Complier综合结果表明，本文改进乘法器相对传统冗余乘法器面积减少8%，延时减少11%。最后，在FPGA上对改进的随机数发生器综合，相比Ziggurat随机数发生器硬件资源减少9.0%、速度提升8.2%；统计检验表明生成的随机数服从高斯分布；将本文随机数发生器应用于蒙特卡罗模拟FPGA硬件加速器中，验证了随机数发生器的有效性。综上所述，本文提出的嵌套分割随机数发生器和改进乘法器可有效减少硬件资源，提高随机数发生器吞吐率，，达到了设计目标。
[Abstract]:The Gauss random number in communication and radar systems, aerospace, pulse ranging, Monte Carlo simulation hardware accelerator is widely used. The Gauss random number generator existing hardware implementation has complicated structure, long design period, this paper improves Ziggurat Gauss random number generator and the fixed-point multiplier, in order to reduce the hardware resources, improve the working frequency of the completion of the research work as follows:
First, the proposed nested segmentation Gauss random number generator Gauss distribution probability density function is divided into top, middle and tail of three sub regions, which were hierarchical nested segmentation, effectively improve the approximation accuracy of the probability density function of the random number, output the maximum value increased from 4.3 to 8.7. after the split in proportion to the random selection of rectangular the area of the probability of a rectangular area, generating probability density function of random points corresponding to rectangular, the abscissa is the Gauss random number output. Based on the improved random number generator overall structure, uniform random number generator module, rear area module, design and Simulation of the key circuit module area at the top..
Second, as an important module multiplier nested partition random number generator, and has an important influence on the performance of the random number generator. The Radix-16 redundant Booth encoding based on the odd times of partial product with redundant differential form, the improved calculation need odd times the multiplicand is reduced from 1 to 0. The improved structure is extended to Radix-32 and the Radix-64 multiplier, the number of odd times of the multiplicand from 3 and 7 respectively reduced to 1, simplifies the control signal generating circuit and a Booth decoding circuit, reducing the use of hardware resources and time delay.
Third, improve the traditional correction method of partial product, and will correct the partial product compression, the number of partial products reduced from 5 to 4. The improved partial product low 7 bit binary conversion circuit at earlier time, simplified binary conversion circuit structure, reduced by Design Complier adder delay and comprehensive results the area under the.TSMC180nm technology show that the improved multiplier multiplier area decreased by 8% compared with the traditional redundancy, reduce the delay of 11%.
Finally, the random number generator comprehensive improvement in FPGA, compared with Ziggurat random number generator hardware resource is reduced by 9%, speed increased by 8.2%; the statistical tests show that the generated random number obeys Gauss distribution; the application of random number generator in Monte Carlo simulation of FPGA hardware accelerator, to verify the effectiveness of the random number generator.
To sum up, the nested split random number generator and improved multiplier proposed in this paper can effectively reduce hardware resources and improve the throughput of random number generator, and achieve the design goal.

【学位授予单位】：华南理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP346;TN791

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