基于珠算原理设计64位除法器及FPGA实现

发布时间：2018-01-04 01:18

本文关键词：基于珠算原理设计64位除法器及FPGA实现　出处：《科学技术与工程》2014年26期 　论文类型：期刊论文

【摘要】：随着数字信号处理的迅猛发展,除法器在计算机和芯片技术发展中受到越来越高的重视。秉承古代数学的操作模型原理,在FPGA平台上设计了一种高性能的64位除法器,将珠算过程的"一列"对应为四位二进制数,利用珠算归除法一次计算可产生四位二进制商,大幅降低关键路径延时。该设计将珠算归除法口诀通过元件例化成五个模块:商位数模块、初商模块、退商模块、撞归模块和补商模块,根据归除原理控制状态机选择模块进行计算。经ISE软件仿真及Xilinx Virtex-2P开发板验证表明,64位珠算除法器的最大工作频率为184 MHz,平均运算仅需0.347 8μs。这适合于对计算能力和速度有较高要求的FPGA设计应用。
[Abstract]:With the rapid development of digital signal processing, divider has been paid more and more attention in the development of computer and chip technology. A high performance 64-bit divider is designed on the FPGA platform. The "one column" of the abacus process is corresponding to the four-digit binary number, and the four-bit binary quotient can be generated by the calculation of the abacus division at one time. The key path delay is greatly reduced. The method of abacus reduction and division is transformed into five modules through element example: quotient module, initial quotient module, retreating quotient module, collision return module and supplementary quotient module. According to the principle of reduction, the selection module of control state machine is calculated, which is verified by ISE software simulation and Xilinx Virtex-2P development board. The maximum operating frequency of the 64-bit abacus divider is 184 MHz, and the average operation is only 0.347 8 渭 s, which is suitable for the FPGA design with high computational power and speed.
【作者单位】：太原理工大学信息工程学院;
【分类号】：TP332.22
【正文快照】： 除法是算数运算中最繁琐且最耗时的运算。目前流行的除法器的设计都是基于移位循环减法原理,以传统移位除法器为代表,其本质是在做减法、比较和移位运算,运算复杂,延时长,工作频率难以提高[1];Xilinx公司仅提供了32位除法器IP核,无法满足更高精度的除法运算需求。本研究秉承中

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