体系结构级Cache功耗优化技术研究

发布时间：2018-01-04 17:02

本文关键词：体系结构级Cache功耗优化技术研究　出处：《浙江大学》2013年博士论文　论文类型：学位论文

【摘要】：随着集成电路制造工艺的进步和微处理器性能的提高,微处理器功耗问题日益严重,成为制约微处理器发展的主要瓶颈。片上高速缓存(Cache)功耗作为微处理器功耗的重要组成部分,降低Cache功耗成为控制微处理器功耗的主要目标。由于底层功耗优化手段受工艺和材料物理特性的制约已经很难满足Cache的功耗约束,因此需要从更高层次对Cache功耗进行优化。本文从Cache功耗的组成、访问特性、功耗性能平衡等多个角度出发,提出了多项体系结构级Cache功耗优化方法。主要研究工作和创新点包括：低功耗指令Cache研究。针对指令Cache行间访问偏移范围存在明显局部性特征,提出了一种将Cache当前访问行及其若干紧邻行链接访问的低功耗指令缓存访问方法。该方法能够在发生相对跳转时依托于相邻行之间的访问链接信息,精确获得跳转目标行的路访问信息,从而减少对Cache标志和数据存储器的访问,达到降低指令Cache动态功耗的目的。在Cache行发生替换时,仅需检测并清除相邻缓存行与被替换行的链接信息,以很小的硬件代价实现链接信息的正确性。低功耗数据Cache研究。针对数据Cache与存储加载队列并行访问的功耗问题和串行访问的性能问题,提出了一种基于存储加载队列预测访问过滤无效数据Cache访问的低功耗方法。利用内存相关性的可预测特征,通过记录加载指令与存储加载队列中存在内存相关性的指令集合,预测后续仅需访问存储加载队列的加载指令,直接从存储加载队列前馈数据通路获取加载结果,关闭数据Cache的访问。 Cache可重构算法研究。针对可重构Cache中重构搜索的开销问题,提出了一种基于函数转移开启Cache重新配置的可重构预测算法。利用函数转移获取新程序段的特性,以函数为单位动态监测Cache缺失率变化,通过函数历史最优Cache配置参数预测后续函数的Cache重构配置信息,减少重构过程对Cache设计空间的搜索；进一步,通过区分重构前后的缓存行,使重构后Cache能够继续使用重构前的缓存数据,降低了Cache初始化的延时和功耗。 Cache无效访问研究。针对分支行为预测错误导致指令Cache的无效访问,提出了一种基于零延时分支预测的指令Cache低功耗方法,利用分支预测的行为信息参与后续分支行为预测,消除深流水、超标量处理器中由于分支代价高导致分支历史重名问题,提高分支行为的预测准确率,减少指令Cache无效访问功耗。本文提出的多项体系结构级Cache功耗优化方法能够在不影响性能的前提下,有效降低Cache功耗,改善微处理器的性能功耗比。
[Abstract]:With the development of integrated circuit and microprocessor performance improvement, microprocessor power consumption is becoming increasingly serious, has become the main bottleneck for the development of microprocessor. The on-chip cache (Cache) power consumption as an important part of microprocessor power consumption, lower power consumption has become the main target of Cache microprocessor to control power consumption. Due to the restriction of power by means of optimization process and bottom the characteristics of composite materials has been difficult to meet the power constraints of Cache, therefore need to optimize power consumption of Cache from a higher level. This article from the composition of Cache power, access characteristics, multi angle performance power balance and so on, put forward a number of system structure Cache power optimization method. The main research work and innovation include:
Low power instruction Cache research. According to the instruction Cache access interline offset range has obvious local characteristics, proposed a low power instruction cache Cache for the current access and several adjacent line link access method. This method can in the relative jump between adjacent rows based on the access link information, precise jump target the way of access to information, thus reducing the Cache signs and data access, to reduce power consumption of instruction Cache dynamic purpose. For Cache substitution, only need to detect and remove adjacent cache line is replaced with the link information, realize the correct link information with little hardware overhead.
Study on Cache data with low power consumption. According to the performance data of Cache and storage load queue parallel access power and serial access, we proposed a prediction filter invalid data Cache access storage load queue based on low power consumption method. The use of memory between predictable characteristics, through the memory load instruction and storage load correlation record the queue in the instruction set, predict the following only access storage loading queue load instruction, obtain loading results directly from the storage load queue feedforward data path, close the Cache data access.
Cache study of reconstruction algorithm. The reconstruction overhead problem in Cache search, proposed a transfer function of open Cache reconfiguration of reconfigurable prediction algorithm based on transfer function. Based on the characteristics of acquiring new program segments, to function as a unit of dynamic monitoring of Cache deletion rate, prediction of Cache reconstruction of configuration information through the following function the historical function of optimal Cache configuration parameters, reduce the search space of the Cache reconstruction process design; further, by distinguishing the cache line before and after the reconstruction, the reconstructed Cache can continue to use the number of cache reconstruction before according to reduced Cache initialization, delay and power consumption.
Study on access invalid Cache. According to the error caused the invalid access instruction Cache branch behavior prediction, proposes a method of low power instruction Cache zero delay branch prediction based on the behavior of information involved in the subsequent branch branch prediction behavior, the elimination of deep water, the amount of processing in the branch history due to exceed the standard problem due to the high cost of the same branch, improve the behavior of branch prediction accuracy, reduce instruction Cache invalid access power.
In this paper, a number of architecture level Cache power optimization methods can effectively reduce Cache power consumption and improve the performance and power consumption of microprocessors without affecting the performance.

【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2013
【分类号】：TP332

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