基于有限状态机的乘法器设计与实现

发布时间：2018-01-04 17:23

本文关键词：基于有限状态机的乘法器设计与实现　出处：《太原科技大学》2012年硕士论文　论文类型：学位论文

【摘要】：乘法器是现代中央处理器、数字信号处理器（DSP）、滤波器等众多现代电子器件中的重要部件。特别在DSP中，乘法器的运算速度几乎决定了DSP的处理速度。因此，乘法器的性能在整个计算系统中起着至关重要的作用。优化乘法器的结构设计，成为改善计算系统整体性能的关键问题。有限状态机对于具有逻辑顺序和时序规律的事件能有清晰的描述，非常适合用来表示乘法这种依靠时序关系进行的操作。因此，本文结合有限状态机分别设计了并行行旁路（PRB）乘法器和有限状态机截断(FSATA)乘法器。（1）根据行旁路乘法器的设计方案，用有限状态机对其设计进行了再现，实验结果表明，，用有限状态机设计的乘法器能够在不降低运算速度的同时显著减少逻辑元件使用数量，使乘法器功耗进一步降低。（2）在行旁路乘法器的基础上进一步优化，提出一种并行行旁路（PRB）乘法器，并用有限状态机进行了实现。在行旁路的基础上，通过对乘数进行重新编码并行输出部分积，使乘法运算中产生的部分积数量减少，提高运算速度；利用有限状态机实现PRB乘法器，有效减少了电路中逻辑元件的数量，降低了功耗。在Quartus平台上进行的仿真表明PRB乘法器在整体性能上有较大的改善。（3）为了实现阵列乘法器设计中影响其整体性能的重要参数——功耗、芯片面积、运算延迟的有效折中，提出一种基于有限状态机的截断（FSATA）乘法器。乘法运算是一系列加法操作来完成的，对乘数和被乘数的关键数据位进行有效地截断处理，可以使部分积的产生更加地灵活。最后，利用有限状态机完成提出的设计，采用VHDL进行编码，在Quartus软件上进行综合与仿真。结果表明相比于采用时序电路完成的设计，FSATA乘法器在延迟上有较优的提高。
[Abstract]:The multiplier is a modern central processor, digital signal processor (DSP), an important component of the filter and many other modern electronic devices. Especially in DSP, the multiplier speed almost determines the processing speed of DSP. Therefore, the multiplier performance plays an important role in the whole calculation system. Structure optimization design of the multiplier, become a key to improve the overall performance of the system. The calculation of finite state machine for logical sequence and timing of events can have a clear description, is suitable to represent the multiplication which rely on temporal relations in operation. Therefore, this paper combined with the finite state machines are designed for parallel bypass (PRB) and the finite state machine (truncated multiplier FSATA) multiplier.
(1) according to the design scheme for bypassing multiplier, the representation of the design by finite state machine. The experimental results show that using the finite state machine design of the multiplier can not reduce the speed of operation while significantly reducing the logic element quantity, the multiplier power consumption is further reduced.
(2) based on the further optimization of row bypassing multiplier, this paper proposes a parallel row bypassing multiplier (PRB), is implemented with finite state machine. Based on the row bypassing multiplier, re encoding parallel output part product, the multiplication of the partial product to reduce the number, improve the operation speed; PRB multiplier using finite state machine, effectively reduces the number of logic elements in the circuit, the power consumption is reduced. Simulation on Quartus platform shows that the PRB multiplier has a great improvement in the overall performance.
(3) in order to realize the important parameters affecting the overall performance of array multiplier design, power consumption, chip area, a trade-off between computation delay, proposes a truncation based on finite state machine (FSATA) multiplier. Multiplication is a series of addition operation to complete, the key data of multiplier and multiplicand effectively truncation, produce can make partial product more flexible. Finally, complete the design using finite state machine, using VHDL encoding, integrated with the Quartus simulation software. The results show that compared with design completed in sequential circuits, the FSATA multiplier has a better improvement in delay.

【学位授予单位】：太原科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.22

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