纳米级下SRAM时序控制电路的鲁棒性研究

发布时间：2018-01-05 05:26

本文关键词：纳米级下SRAM时序控制电路的鲁棒性研究　出处：《安徽大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着移动通信技术,3D技术,GPS导航技术,高速无线网络技术的迅速发展,推动了现代集成电路设计追求更高的工艺水平。片上系统中嵌入式的Memory等存储器已成为芯片设计的重要组成部分,预计到2017年片上Memory面积的百分比将达到90%以上。片上存储器面积的增加、工艺偏差的增加以及电源电压降低都使得片上存储器的设计面临巨大的挑战。静态随机存储器(Static Random Access Memory,简称:SRAM)因其高速、低功耗的特性被广泛应用于手机,个人电脑等电子产品,因此,SRAM的性能将直接影响到SOC芯片的性能。晶体管阈值电压(Vth)的工艺偏差将对SRAM的稳定性和访问时间造成很大的影响。针对这一问题,本文深入研究了工艺、电压、温度(简称:PVT)对于SRAM稳定性的影响并提出了两种更加有效的改进技术,主要内容如下:首先介绍了 SRAM主要的几大结构,包括存储阵列、灵敏放大器、译码器、读写控制电路等结构,并重点介绍了存储阵列结构以及灵敏放大器的工作原理,然后分析了 SRAM读操作的原理。接着介绍了两种时序控制技术(反相器链延时技术和传统复制位线技术),并对这两种技术进行了对比,得出了复制位线技术更有优势的结论。接着介绍了近年来国内外的研究人员对SRAM时序控制电路进行的一些改进设计,重点介绍分析了其中的3种设计方案,分别是:数字复制位线技术、多级双复制位线技术以及双列交错复制位线技术,对它们的结构和原理进行了深入分析,并做了一定的理论推导,并通过蒙特卡罗仿真与传统复制位线技术进行了对比。最后,本文提出了两种改进技术,第一种是双列复制位线技术,第二种是基于自举电路的复制位线技术,在以往的改进设计中,都是从复制位线结构本身来改进,而本文提出的第二种方案从复制位线的外围电路中进行了改进,在不大量增加面积开销的前提下,经仿真结果显示,该方案取得了很好的改善效果。
[Abstract]:With the rapid development of mobile communication technology and GPS navigation technology, high-speed wireless network technology is developing rapidly. It promotes the modern IC design to pursue a higher level of technology. The embedded memory such as Memory in the on-chip system has become an important part of the chip design. It is expected that by 2017, the percentage of Memory area on the chip will be more than 90%. The area of on-chip memory will increase. The increase of process deviation and the decrease of power supply voltage make the design of on-chip memory face great challenge. Static Random Access Memory. Because of its high speed and low power consumption, it is widely used in electronic products such as mobile phones, personal computers and so on. The performance of SRAM will directly affect the performance of SOC chip. The process deviation of transistor threshold voltage will greatly affect the stability and access time of SRAM. In this paper, the effects of process, voltage and temperature on the stability of SRAM are studied and two more effective techniques are proposed. The main contents are as follows: firstly, several main structures of SRAM are introduced, including memory array, sensitive amplifier, decoder, read / write control circuit and so on. The structure of the memory array and the working principle of the sensitive amplifier are introduced in detail. Then the principle of SRAM read operation is analyzed, and then two kinds of timing control techniques (inverter chain delay technique and traditional copy bit line technique) are introduced, and the two techniques are compared. The conclusion that duplication bit line technology has more advantages is obtained. Then some improved designs of SRAM sequential control circuit are introduced by researchers at home and abroad in recent years. This paper mainly introduces and analyzes three design schemes, which are digital copy bit line technology, multilevel double copy bit line technology and double row interleaved replication bit line technology, and analyzes their structure and principle. Finally, this paper proposes two improved techniques, the first one is double-row replication bit line technology. The second is based on bootstrap circuit replication bit line technology, in the past improvement design, is from the replication bit line structure itself to improve. The second scheme proposed in this paper is improved from the peripheral circuit of the replica bit line. The simulation results show that the scheme has a good effect without increasing the area overhead.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333

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