SoC总线的低功耗分支编码方案

发布时间：2018-01-05 07:25

本文关键词：SoC总线的低功耗分支编码方案　出处：《计算机应用》2014年12期 　论文类型：期刊论文

【摘要】：为了降低So C总线功耗,提出一种总线低功耗分支编码。该编码的基本思想为:对于地址总线,当地址连续时将地址总线死锁,当地址不连续时动态地调整窗口大小对其进行翻转编码;对于数据总线,对不同数据位宽分别设置两个汉明距阈值,当汉明距落在两个阈值之间则查找有效数据通道翻转密集区并对该区取反,两个阈值之外则采用翻转编码。该方法的编解码电路在32位AHB总线系统上实现,实验证明该方法与未编码之前相比将地址总线跳变率降低了51.2%,数据总线跳变率降低了22.4%,系统总功耗降低了28.9%。将T0编码、BI编码等方法在相同系统下实现后与所提方法作比较,证明分支编码方法在降低跳变率和功耗上有明显的优势。
[Abstract]:In order to reduce the power consumption of the So C bus, a bus low power branch encoding. The basic idea is: for encoding the address bus, the address bus address when continuous deadlock when the address is not continuous, dynamically adjust the window size of the flip encoding for the data; total line of different data width were set two a Hamming distance threshold, when the Hamming distance falls between the two threshold to find effective channels of data intensive areas and flip the area beyond the two threshold is used to invert encoding decoding circuit. The implementation of the method in the 32 bit AHB bus system, and the experimental results prove that this method is not prior to the address encoding the bus jump rate is reduced by 51.2% and the data bus jump rate is reduced by 22.4%, the total power consumption of the system reduces the 28.9%. T0 encoding, BI encoding method is implemented in the same system and the proposed method compares the proof encoding branch The method has obvious advantages in reducing the rate of jump and power consumption.

【作者单位】：西安交通大学电子与信息工程学院;北京大学软件与微电子学院;
【基金】：国家自然科学基金资助项目(61172041)
【分类号】：TP336
【正文快照】： 0引言在片上系统(System on Chip,So C)中,会包含相当数量的总线,总线会带来大负载、长连线、大电阻效应等。总线的功耗要占到整个芯片总功耗的相当大一部分,动态功耗是总线功耗大小的决定性因素,而动态功耗和开关活动性息息相关。若信号活动性为0,即使负载电容很大,它也不消

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