数据驱动异步微处理器设计关键技术研究

发布时间：2018-01-09 11:29

本文关键词：数据驱动异步微处理器设计关键技术研究　出处：《国防科学技术大学》2012年博士论文　论文类型：学位论文

【摘要】：随着半导体工艺尺寸的不断减小,单个芯片上可以集成的晶体管数目越来越多,同步电路设计遇到的时钟偏差、功耗过大以及可靠性降低等问题也日益突出。异步电路使用本地握手信号来控制电路各模块操作的时序,从根本上解决了同步电路设计面临的问题。相对同步电路而言,异步电路具有功耗低、性能好、鲁棒性高和电磁兼容性好等优势。因此,异步电路技术在未来微处理器发展过程中的应用将越来越广泛。目前,异步微处理器设计发展仍面临诸多挑战,其中最主要是缺少相应的CAD工具的支持。本文针对数据驱动异步微处理器设计与分析中的关键问题,对数据驱动异步电路中的关键路径分析、死锁检测、模拟评估、粗粒度数据驱动异步电路设计流程等关键技术进行了广泛而深入的研究,并实现了数据驱动异步微处理器原型,取得的主要研究成果包括： 1.提出了一种自动化的数据驱动异步电路关键路径分析方法。基于数据驱动异步电路设计工具Teak,利用异步电路模块化特点,在部件级和门级分别进行分析,利用宽度优先搜索算法将电路中的组合环路打开,然后采用多源最长路径算法分析出相邻锁存器之间的路径长度,根据关键路径阀值来确定关键路径。该分析方法可以在多项式时间内对数据驱动异步电路中的延迟分布情况进行自动化分析。在关键路径分析基础上实现了一种基于关键路径的锁存器插入方法,实验结果表明该锁存器插入方法有效提高了电路的吞吐率 2.提出了一种基于结构的数据驱动异步电路死锁检测方法。针对传统异步电路死锁检测方法面临的状态空间爆炸问题,本文通过分析电路的结构特征,而非电路的状态特征,给出无死锁的良定义Steer-Merge-Fork-Join (SMFJ)部件网络的结构特征,并确定良定义SMFJ部件网络的充要条件。同时,本文分析了SMFJ部件网络中通道的Slack弹性,为SMFJ部件网络引入流水机制。最后,在数据驱动异步电路设计工具Teak中实现了一种自动化的死锁检测方法。实验结果表明,基于结构的死锁检测方法与传统的基于状态空间的方法相比具有明显的检测效率优势。 3.提出了一种基于事件行为模型的数据驱动异步电路模拟评估方法。对电路性能进行验证评估最直接的途径就是模拟,然而目前还没有专门针对异步电路的模拟评估工具,设计者往往采用同步模拟工具对异步电路在设计后期进行模拟,其时间开销很大。本文针对数据驱动异步电路提出事件行为模型,该模型构造过程中包含有门级延迟信息。基于该模型实现了一款事件驱动模拟器ESim用于对异步电路的模拟和性能评估。同时,根据模拟过程中的执行轨迹,实现了对异步电路性能的优化。实验表明,ESim模拟器可以对电路性能进行快速评估,并且在异步电路性能优化方面具有很强的指导意义。 4.提出了一种粗粒度的数据驱动异步电路设计流程。本文融合之前提出的关键路径分析、死锁检测和模拟评估技术,提出一套完整的粗粒度数据驱动异步电路设计流程。与语法指导的异步电路设计流程不同,该流程基于基本数据驱动部件,聚合数据处理部件,实现一种粗粒度的控制模式,简化了电路中的控制开销,提高了电路性能。同时,该流程与基于同步电路设计的流程不同,采用本文流程实现的异步电路不需要进行延迟匹配,保持了异步电路的准延迟无关特性,具有良好的鲁棒性。为了验证粗粒度数据驱动异步电路设计流程及其关键支撑技术的可行性和有效性,本文基于该流程实现了一款安全异步微处理器原型NanoSpa,其中运用了关键路径分析技术、基于结构的死锁检测技术以及基于事件行为模型的高层模拟评估技术等,实验结果表明使用粗粒度数据驱动异步电路设计流程可以实现高效能的异步微处理器。
[Abstract]:With the decreasing size of semiconductor technology , the number of transistors that can be integrated on a single chip is more and more , and the problems such as clock deviation , excessive power consumption and lower reliability of synchronous circuit design are becoming more and more prominent . The asynchronous circuit has the advantages of low power consumption , good performance , high robustness and good electromagnetic compatibility . Aiming at the key problems in the design and analysis of data - driven asynchronous microprocessor , the key technologies such as key path analysis , deadlock detection , simulation evaluation , coarse - grained data - driven asynchronous circuit design flow in data - driven asynchronous circuits have been studied extensively , and the data - driven asynchronous microprocessor prototype has been realized . The main research results are as follows : 1 . An automatic data - driven asynchronous circuit - critical path analysis method is presented . Based on the data - driven asynchronous circuit design tool , the component - level and gate - level are analyzed by using the modularization feature of the asynchronous circuit . The path length between adjacent latches is analyzed by using a multi - source longest path algorithm . A key path - based latch insertion method is implemented based on the key path analysis . The experimental results show that the latch insertion method effectively improves the throughput rate of the circuit . 2 . A structure - based deadlock detection method for data - driven asynchronous circuits is presented . In this paper , the structural characteristics of the network of SMFJ parts are analyzed by analyzing the structural characteristics of the circuit and the state characteristics of the non - circuit . At the same time , the paper analyzes the Slack elasticity of the channel in the SMFJ component network and introduces a flow mechanism for SMFJ component networks . 3 . A data driven asynchronous circuit simulation evaluation method based on event behavior model is presented . The most direct way to evaluate the circuit performance is to simulate the asynchronous circuit . 4 . A coarse - grained data - driven asynchronous circuit design flow is put forward . The key path analysis , deadlock detection and simulation evaluation techniques presented before the integration of this paper propose a complete set of coarse - grained data - driven asynchronous circuit design flow , which is based on basic data - driven parts , aggregation data - processing parts , implements a coarse - grained control mode , simplifies the control overhead in the circuit and improves the circuit performance . In order to verify the feasibility and effectiveness of coarse - grained data - driven asynchronous circuit design flow and its key support technology , this paper implements a secure asynchronous microprocessor prototype NanoSpa based on this process , in which the key path analysis technology , structure - based deadlock detection technology and high - level simulation evaluation technology based on event behavior model are used . The experimental results show that the asynchronous circuit design flow can be driven by coarse - grained data to realize high - efficiency asynchronous microprocessor .

【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2012
【分类号】：TP332

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