先进微处理器高密度封装协同设计与仿真技术研究

发布时间：2018-01-09 23:15

本文关键词：先进微处理器高密度封装协同设计与仿真技术研究　出处：《国防科学技术大学》2013年硕士论文　论文类型：学位论文

【摘要】：封装是微处理器的重要组成部分，它作为芯片与外界的连接桥梁，对于整个系统的性能发挥具有非常重要的作用。随着集成电路技术的发展，现代先进微处理器的输入输出接口快速增长，使得封装呈现出高密度的特点。传统的封装设计方法逐渐显露出设计难度增大、无法达到设计要求和过设计等问题，成为限制微处理器设计发展的一个瓶颈。本文基于“核高基”重大专项高性能微处理器项目，针对先进微处理器高密度封装设计中存在的问题，研究协同设计与仿真技术，分别研究了多阶段协同、信号与电源完整性协同和设计与仿真协同技术，具体包括： (1)封装驱动的多阶段协同设计规划。针对传统设计方法中芯片、封装和电路板独立设计存在的不足，本文提出将三者作为一个整体协同设计，，并以封装为中心对系统进行统一的引脚分配，以解决信号引脚分配不合理、走线不顺、布局混乱等问题。 (2)基于叠层规划的信号与电源协同设计。高密度封装中信号与电源的相互影响愈加严重，本文提出在叠层规划中同时考虑信号完整性和电源完整性，对信号和电源进行协同设计，减小在封装设计中信号与电源相互影响，使二者达到最佳。 (3)面向封装的设计与仿真协同优化。为了解决传统设计中使用经验法则等粗放型设计方法存在的不足，本文提出将设计与仿真紧密结合，在设计之初通过仿真制定准确的设计规则和目标，在设计之后用仿真验证设计，通过精细化方法解决欠设计和过设计问题。基于以上协同设计方法，本文设计实现了一款先进微处理器的高密度封装。该处理器主要包括DDR3、PCIE、SATA等12种接口和7种电源，芯片引脚数达到4733。采用本文提出的方法，设计实现了尺寸为42.5mm×42.5mm和封装引脚为1572个的处理器芯片封装。实测结果表明，该封装芯片可稳定工作在1.2GHz，DDR、PCIE和SATA速率分别达到1333Mbps、5.0Gbps和3.0Gbps，实现了设计目标。
[Abstract]:Packaging is an important part of the microprocessor, it used as a bridge connecting the chip with the outside world, it is very important for the performance of the whole system. With the development of integrated circuit technology, input and output interface of modern microprocessors with the rapid growth of the package shows the characteristics of high density packaging. The traditional design method gradually revealed the design difficulty increases, cannot meet the design requirements and design, has become a bottleneck restricting the development of microprocessor design.
This paper is based on "nuclear high base" major special high performance microprocessor project, aiming at the existing advanced microprocessor high density packaging design problems, research on collaborative design and simulation technology, studied multi stage coordination, signal and power integrity and collaborative design and Simulation of collaborative technology, including:
(1) multi stage package driven collaborative design planning. According to the traditional design method of chip package and circuit board, lack of independent design, this paper put forward the three as a whole collaborative design, and the center pin package for the uniform distribution of the system, to solve the unreasonable distribution of signal pins, go the line is not smooth, layout confusion and other issues.
(2) collaborative design. The signal and power supply layer planning based on interaction of the signal and the power of high density packaging in the increasingly serious, proposed in the laminated planning considering signal integrity and power integrity, collaborative design of signal and power, decreases in the package design of signal and power influence each other. The two is the best.
(3) the design and Simulation for package collaborative optimization. In order to solve the shortcomings of traditional design in the use of the principle of extensive design methods are proposed in this paper, combining with design and simulation, at the beginning of the design by simulation to develop accurate design rules and goals, verify the design by simulation in the design, to solve the lack of design and the design problem through the refinement method.
Based on the above method of collaborative design, this paper design a high density packaging advanced microprocessor. The processor mainly includes DDR3, PCIE, SATA and other 12 kinds of interface and 7 kinds of power supply, chip pin number reached 4733. by the method presented in this paper, the design and implementation of the processor chip package size is 42.5mm * 42.5mm and 1572 pin package a. Experimental results show that the chip can work stably in 1.2GHz, DDR, PCIE and SATA rate were respectively 1333Mbps, 5.0Gbps and 3.0Gbps, to achieve the design goals.

【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TN405

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