基于LSI的多种类ISA处理器平台设计与研究

发布时间：2018-01-12 04:02

  本文关键词：基于LSI的多种类ISA处理器平台设计与研究　出处：《南京大学》2012年硕士论文　论文类型：学位论文

  更多相关文章： ISA处理器 LSI FPGA Wishbone

【摘要】：随着社会的不断发展,不仅在工业生产,而且在人们的普通生活中,对于精密控制的需求越来越大。而传统ISA处理器由于其内部有限的逻辑资源和外部固定的引脚封装,大大的限制了它的应用范围。由于市场上有着各具特色的微处理器,为了能很好的学习它们,我们不得不购买大量不同的平台,造成资源的浪费。 本文首先通过详细的分析传统的微处理器组成结构、存储器组织结构和指令集结构,使我们对于处理器工作原理有了明确的认识。接着分析基于LSI的可编程ASIC器件FPGA的内部结构,发现我们可以充分利用FPGA丰富的逻辑资源来实现传统MCU中的各个组成部分,而它的可配置引脚将会帮助降低硬件设计复杂度,最后我们论述了Wishbone总线结构,用来作为各个模块间相互连接总线。 使用该种方式构建系统,对于上层软件工程师而言其编程操作与标准MCU相一致,而对于底层可以自由配置IO引脚,获得最大的硬件自由度。我们采用了片内总线设计,因此我们可以依据自己的需求,定制自己的系统,如增加各种外设,以达到传统MCU所无法完成的要求。对于高校,可以使用这种方法来进行教学实验,能够让学生深入的理解MCU中每个组成部分的功能和它的连接方式,同时也不会造成硬件损坏。 本文使用硬件描述语言Verilog和VHDL,自底向上设计MIPS、8086、80C51和AVR处理核心,并且与几类通用外设互连组成系统,使用Virtex-Ⅱ Pro系歹FPGA进行板级验证。板级验证结果,表明我们实现既定目标,与标准MCU兼容,系统运行稳定。
[Abstract]:With the continuous development of society, not only in industrial production, but also in the ordinary life of people. The demand for precision control is increasing, while the traditional ISA processor is encapsulated because of its limited internal logic resources and external fixed pins. Because of the unique microprocessor in the market, in order to learn them well, we have to buy a large number of different platforms, resulting in a waste of resources. Firstly, this paper analyzes the traditional microprocessor structure, memory organization structure and instruction set structure in detail. So that we have a clear understanding of the working principle of the processor. Then the internal structure of the programmable ASIC device FPGA based on LSI is analyzed. It is found that we can make full use of the rich logic resources of FPGA to realize each component of traditional MCU, and its configurable pin will help reduce the complexity of hardware design. Finally, we discuss the structure of Wishbone bus, which is used to connect each module to each other. Building systems in this way is consistent with standard MCU programming for upper software engineers and free to configure IO pins for the bottom layer. Get the maximum degree of freedom of hardware. We use an in-chip bus design, so we can customize our own system according to our own needs, such as adding a variety of peripherals. In order to achieve the traditional MCU can not complete the requirements. For colleges and universities, we can use this method to carry out teaching experiments, so that students can deeply understand the function of each component of MCU and its connection. Also does not cause hardware damage. In this paper, we use hardware description languages Verilog and VHDL to design the MIPS 8086 / 80C51 and AVR processing cores from the bottom up, and interconnect with several kinds of general peripheral devices to make up the system. Using Virtex- 鈪，

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