基于2T GC的动态随机存储器版图设计及其关键参数表征与优化

发布时间：2018-01-15 04:19

本文关键词：基于2T GC的动态随机存储器版图设计及其关键参数表征与优化　出处：《复旦大学》2012年硕士论文　论文类型：学位论文

【摘要】：本文基于一种新型嵌入式动态随机存储器2T GC的版图设计和关键参数进行了相关的研究工作。2T GC存储器版图设计是影响2T GC面积的重要因素,同时还涉及到面积与性能及功耗的折中问题。其中包含了2T GC单元的版图设计和优化,主要考虑单元版图对存储密度和存储性能的影响；阵列和行列驱动电路版图设计,主要考虑大规模阵列的层次划分问题以及存储阵列与外围电路的拼接匹配；其它外围电路版图的布局和设计,主要考虑各个模块的布局以及大规模版图设计时需要考虑的各种问题。保持电流和数据保持时间是影响2T GC静态保持功耗和性能的两个主要参数,而且在新工艺代下漏电流和波动性问题日益凸显,本文基于65nm工艺代针对2T GC的两大关键参数保持漏电流和数据保持时间波动性的表征问题进行了研究,其中对保持电流的研究主要包括单元保持漏电的来源分析,以及阵列和单元保持漏电表征方案及单元保持漏电的优化方案分析,同时将提出的表征方案应用于静态随机存储器SRAM的单元漏电表征。2T GC是动态随机存储器即需要周期性刷新,而刷新周期则是由单元的数据保持时间决定的,所以2T GC数据保持时间是影响刷新功耗和存储性能的重要参数,而在新工艺代下此参数受PVT工艺波动影响会产生相应的波动变化,为了研究此波动情况从而给芯片设计参数制定提供指导本文提出了一种表征2T GC数据保持时间波动性的方案。本文最终基于SMIC0.13um工艺实现了一款128kb的2T GC存储器芯片,经过验证具有正确的读写功能；同时本文还基于SMIC65nm工艺实现了2T GC单元保持漏电和数据保持时间的表征。
[Abstract]:The layout design and the key parameters of a new embedded dynamic random access memory 2T based on GC the design work of.2T GC memory layout is an important factor that affects the 2T GC area, but also involves a tradeoff between area and performance and power consumption. Which includes the design and optimization of the layout of 2T GC unit, the main consideration effect of storage cell layout density and storage performance; circuit layout design drive array and ranks, mainly consider the hierarchy of large-scale array and splicing memory array and peripheral circuit, other peripheral circuit layout; layout and design, all kinds of problems need to be considered the main consideration of each module layout and scale layout design. The current and the data retention time are two main parameters affecting 2T GC static power consumption and performance, but also in the process of the new generation Leakage current and volatility problems have become increasingly prominent, the 65nm process on behalf of two key parameters for 2T GC to keep the leakage current and maintain data representation of time variability was studied based on the research to maintain the current mainly includes the analysis of leakage source unit remains, and keep the unit array and the leakage characterization scheme and unit analysis of optimization scheme of leakage, while the proposed characterization scheme is applied to static random access memory SRAM cell leakage characterization of.2T GC dynamic random access memory that requires periodic refresh, refresh cycle is from the unit and the data retention time of decision, so 2T GC data hold time is an important parameter affecting the refresh power and storage performance in the process, the new generation of the parameters affected by PVT process fluctuations will produce fluctuations corresponding to the situation, so as to study the fluctuation of chip The design parameter formulation provides guidance and proposes a scheme to characterize the time volatility of 2T GC data retention.
Finally, a 128KB 2T GC memory chip is implemented based on SMIC0.13um technology. After verification, it has the correct read and write function. At the same time, based on the SMIC65nm technology, the 2T GC unit maintains the leakage and data retention time.

【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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