浮点运算加速器的设计研究

发布时间：2018-01-15 06:28

本文关键词：浮点运算加速器的设计研究　出处：《浙江大学》2013年硕士论文　论文类型：学位论文

【摘要】：信息社会的发展使得科学研究、工业生产、人工智能以及3D游戏等应用都对浮点运算性能提出了更高的要求。因此低延迟高吞吐的浮点数运算单元是各类处理器设计中的关键部件。在研究了传统的浮点加法器,浮点乘法器以及浮点融合乘加器的架构与实现方法后,本文基于一种单周期累加算法,改进了浮点运算单元的经典结构,在流水线中添加一条累加环路,通过进位保留算法使最终求和与规格化模块后置,实现了可在一个周期内完成浮点加法运算的累加模块,大幅提高了运算单元处理向量点乘时的效率,达到每周期一次浮点乘加。同时为了满足更多场合的需求,采用资源复用的设计支持SIMD运算,使其兼容双精度浮点数、两组单精度浮点数,32位有符号数以及两组16位有符号数,可执行加法,乘法,融合乘加和连续乘累加四种操作,并对乘法器、前导零检测等模块做了优化,以降低延迟与面积。最后针对该结构的数据流特性,采取了操作数隔离与门控时钟的低功耗技术。本文采用SystemVerilog语言搭建验证平台,生成带约束的随机测试向量并自动检验结果,保证了代码覆盖率的要求。在SMIC0.13um的逻辑工艺下频率达到400MHz,电路规模等效于58.4k个与非门。通过门级网表仿真得出加入低功耗设计后动态功耗为54.8mW,降低了24.1%。
[Abstract]:With the development of information society, the applications of scientific research, industrial production, AI and 3D games have raised higher requirements for the performance of floating-point operation. Therefore, the floating point arithmetic units with low latency and high throughput are the key components in the design of all kinds of processors.
In the study of traditional floating point adder, and the realization method of Floating-Point Multiplier and floating point multiply add fused device structure, in this paper, a single cycle accumulation algorithm based on improved classical structure of FPU, add a loop accumulated in the pipeline, carry through retention so that the final sum algorithm module and post specifications the module can be completed, the cumulative floating point addition operation in a period, a substantial increase in the operational efficiency of the unit vector multiplication per cycle, a floating point multiply add. At the same time in order to meet the needs of more occasions, the design resource reuse support SIMD operations, making it compatible with double precision floating-point number. Two sets of single precision floating point, 32 of the number of symbols and two sets of 16 of the number of symbols, can perform addition, multiplication, multiply add fused and continuous multiply accumulate four kinds of operation, and the multiplier, lead zero detection module Optimization is done to reduce the delay and area. Finally, in view of the data flow characteristics of the structure, the low power technology of operating number isolation and gating clock is adopted.
The verification platform is constructed using SystemVerilog language to generate constrained random test vectors and automatic inspection results, ensure the code coverage requirements. In the logic process of SMIC0.13um under the frequency of 400MHz, the circuit scale is equivalent to the 58.4k NAND gate level netlist. Through simulation to low power design of dynamic power consumption of 54.8mW, reduce the 24.1%.

【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332.2

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