DSP处理器中数据Cache的设计和验证

发布时间：2018-01-15 12:07

本文关键词：DSP处理器中数据Cache的设计和验证　出处：《西安电子科技大学》2013年硕士论文　论文类型：学位论文

【摘要】：Cache能够提高DSP处理器对外部存储器的存取速度，提高DSP的性能。不过，由于Cache面积大，访问频率高，是DSP芯片的主要功耗来源。设计高性能低功耗的Cache，对于提高DSP芯片的整体性能有着十分重大的意义，是目前DSP设计中的热点问题。本文设计了一种高性能低功耗的数据Cache。这种Cache是通过增加具备重装功能的Line Buffer来减少处理器对Cache的访问频率，从而降低Cache功耗。论文首先根据应用需求确定了Cache的参数指标，，进行了系统架构设计，在此基础上，使用硬件描述语言VHDL对数据Cache模块进行了自顶向下的设计实现，最后使用Synopsis公司的VCS软件对本文设计的Cache进行了模拟仿真，结果表明：数据Cache的存在使得系统发生缺失时，能在6个时钟周期内完成将片外存储器中数据送入DSP处理器，并在20个周期内完成Cache Line的替换，整个数据Cache的设计结果实现预期功能，满足路径延时要求，可极大提高DSP性能。通过FFT，AC3，FIR三种基准程序测试表明，Line Buffer可以降低35%的Cache访问频率，明显降低了数据Cache功耗。目前该数据Cache已经投入使用，并能保证其整体功耗在0.5mW/MIPS内。
[Abstract]:Cache can improve the access speed of DSP processor to external memory and improve the performance of DSP. However, because of the large area of Cache, the access frequency is high. The design of DSP chip with high performance and low power consumption is of great significance to improve the overall performance of DSP chip and is a hot issue in DSP design. This paper designs a high performance and low power data Cache. this Cache is designed by adding a reload Line. Buffer to reduce processor access to Cache. Thus, the power consumption of Cache is reduced. Firstly, the parameter index of Cache is determined according to the application requirement, and the system architecture is designed. The data Cache module is designed and implemented from top to bottom by using the hardware description language VHDL. Finally, the Cache designed in this paper is simulated with the VCS software of Synopsis Company. The results show that the existence of data Cache results in the absence of the system. Data in off-chip memory can be fed into the DSP processor in 6 clock cycles, and the replacement of Cache Line can be completed in 20 cycles. The design result of the whole data Cache realizes the expected function, satisfies the path delay request, and can greatly improve the DSP performance. The results of three kinds of FFT / AC3 / Fir programs show that Line Buffer can reduce the frequency of Cache access by 35%. The data Cache power consumption has been significantly reduced. The data Cache has been put into use and can ensure its overall power consumption within 0.5 MW / MIPS.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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