C程序映射到FPGA的寄存器快速评估技术

发布时间：2018-01-16 03:29

  本文关键词：C程序映射到FPGA的寄存器快速评估技术　出处：《小型微型计算机系统》2015年02期 　论文类型：期刊论文

  更多相关文章： FPGA 高级综合 逻辑综合 设计度量 寄存器快速评估

【摘要】：在基于FPGA的软硬件协同设计中,对硬件面积和延迟时间进行快速准确地评估是快速生成片上异构多处理器系统的关键步骤.使用传统的逻辑综合工具将会耗费大量的时间才能获得面积-时间的度量值,导致在软硬件协同设计流程中,抑制了设计空间的有效探索.本文关注将C程序映射到FPGA,对寄存器数量进行快速和准确的评估.提出的技术以高级综合工具Leg Up和底层虚拟机LLVM为基础,利用信号位宽优化信息、特殊指令信息以及编码方式对寄存器进行评估.实验结果表明,该技术能够对CHStone基准测试程序进行寄存器数量的评估;以Altera CycloneⅡ和StratixⅣFPGA为平台,实验结果的误差分别只有13.75%和10.48%,与使用Quartus工具的逻辑综合运行时间相比,能够实现84倍的加速.
[Abstract]:In the hardware and software co-design based on FPGA. Fast and accurate evaluation of hardware area and delay time is a key step in fast generation of heterogeneous multiprocessor systems on a chip. Using traditional logic synthesis tools will take a lot of time to obtain area-time. Measure. As a result of hardware and software co-design process, the effective exploration of design space is restrained. This paper focuses on mapping C program to FPGA. The proposed technology is based on the advanced synthesis tool Leg up and the underlying virtual machine LLVM, and optimizes the information by using the signal bit width. The special instruction information and coding method are used to evaluate the register. The experimental results show that this technique can evaluate the number of registers for the CHStone benchmark program. Using Altera Cyclone 鈪，

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