基于DVS的多核周期任务节能调度策略研究

发布时间：2018-01-17 13:11

  本文关键词：基于DVS的多核周期任务节能调度策略研究　出处：《武汉理工大学》2013年硕士论文　论文类型：学位论文

  更多相关文章： 多核处理器 节能调度算法 动态电压调节 空闲时间

【摘要】：近年来,多核处理器在流媒体和高性能计算领域应用广泛。多核处理器与单核处理器相比带来了更高的性能,但同时也带来了更多的能耗,较高的能量消耗会导致处理器热量的增加及系统可靠性的降低。节能性要求也必然存在于多核计算平台上的应用之中。 处理器能耗占系统总能耗的一半以上,处理器的能耗主要由动态能耗和静态泄露能耗构成,一般情况下,动态能耗占处理器总能耗的70%左右。根据当前任务的能量消耗特性和多核系统结构,在满足系统可靠性和截止期约束的前提下,如何减少能量消耗已成为多核处理器实时节能调度研究领域的热点。 本文主要工作如下： (1)基于处理器核负载总均衡的思想,提出了PWBP任务映射策略,该策略将任务队列中的任务按任务利用率从大到小排序,抽取前M个任务并将这M个任务轮询映射到M个处理器核上,剩余的任务按顺序映射到当时负载最小的处理器核直至任务映射完成,此策略的核心思想是保持处理器核的总负载均衡,仿真实验表明该映射策略与其他映射策略相比有更好的节能效果；然后,基于周期任务的静态空闲时间SST提出了MSSF最大静态空闲时间优先排序策略,在利用DVS技术回收动态空闲时间之前,该策略对映射到处理器上的任务按静态空闲时间SST的大小进行重新排序,在单核处理器中,将MSSF排序策略与现有GSSR策略和STF策略对比,仿真实验结果表明了MSSF排序策略的优越性。 (2)结合DVS技术中的HR2混合调度法,提出了PWBP-DSR节能调度算法,并根据最小关键速度Scritical增加了处理器速度判断机制：当处理器的速度S≤scritical时让处理器的执行速度S=Scritical如果处理器的速度ScriticalS≤1时,则处理器按当前速度S执行任务。在此速度判断机制的基础上提出了改进算法PWBP-DSR-M,将提出的改进算法PWBP-DSR-M与参考文献算法GEDF-OLEASA(ALL)和GEDF-OLEASA(EACH)对比,实验结果表明提出的改进算法比其他两种对比算法节能将近10%。
[Abstract]:In recent years, multicore processors have been widely used in streaming media and high-performance computing. Compared with single-core processors, multi-core processors bring higher performance, but also bring more energy consumption. Higher energy consumption will lead to the increase of processor heat and the decrease of system reliability. The requirement of energy saving must also exist in the application of multi-core computing platform. Processor energy consumption accounts for more than half of the total energy consumption of the system, the processor energy consumption is mainly composed of dynamic energy consumption and static leakage energy consumption, generally speaking. The dynamic energy consumption accounts for about 70% of the total energy consumption of the processor. According to the energy consumption characteristics of the current task and the multi-core system structure, the system reliability and deadline constraints are satisfied. How to reduce energy consumption has become a hotspot in the field of real-time energy-saving scheduling of multi-core processors. The main work of this paper is as follows: 1) based on the idea of total load balance of processor core, a PWBP task mapping strategy is proposed, which sorts the tasks in the task queue from large to small according to the task utilization. The first M tasks are extracted and the M tasks are polled onto M processor cores, and the remaining tasks are mapped sequentially to the processor cores with the smallest load at that time until the task mapping is completed. The core idea of this strategy is to maintain the total load balance of the processor core. The simulation results show that the mapping strategy has better energy saving effect than other mapping strategies. Then, the static idle time SST based on periodic task proposes the MSSF maximum static idle time priority ranking strategy, before using the DVS technology to recover the dynamic idle time. The policy reorders tasks mapped to the processor by the size of the static idle time SST, and compares the MSSF sort policy with the existing GSSR policy and the STF policy in a single core processor. Simulation results show the superiority of MSSF scheduling strategy. 2) combined with the HR2 hybrid scheduling method in DVS technology, a PWBP-DSR energy-saving scheduling algorithm is proposed. According to the minimum critical speed Scritical, the processor speed judgment mechanism is added. When the processor's speed S 鈮，

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