基于FPGA的32位五级流水线CPU的研究与设计

发布时间：2018-01-18 06:30

本文关键词：基于FPGA的32位五级流水线CPU的研究与设计　出处：《河北工业大学》2012年硕士论文　论文类型：学位论文

更多相关文章： FPGA 流水线 CPU Verilog HDL

【摘要】：目前，国内大部分高校的计算机组成实验平台是纯硬件化的，内部结构固定，灵活性差，不利于学生自主创新，大大降低了教学质量。FPGA技术提供了一个灵活的设计平台，本论文采用FPGA技术，设计了32位五级流水线CPU，可应用于计算机组成实验课程，有助于提高教学质量。论文根据实际需要，结合理论研究，提出了基于FPGA的五级流水线CPU的总体结构模型，利用DE2开发平台完成了32位五级流水线CPU的设计过程，实现了取指IF、指令译码ID、指令执行EXE、存储MEM和结果写回WB五个周期的功能设计，并专门设计了流水线演示系统，通过对系统演示效果的分析，验证了CPU设计的合理性。论文采用Verilog HDL语言，完成了流水线CPU五个周期的设计。取指周期设计了PC寄存器和指令存储器，实现了取指令功能；译码周期设计了控制器CU、寄存器堆等部件，完成了20条指令的译码功能；指令执行周期主要对运算器ALU的设计，实现了对数据的运算操作；存储周期完成了数据存储器的设计，用于存储周期的读写操作；结果写回周期，通过设计多路器，实现将正确的结果写回到目的寄存器中。流水线的设计，必然带来相关问题，含有数据相关、控制相关和结构相关。论文重点对前两种相关进行了研究与处理，，设计了内部前推方法和暂停流水方法相结合的策略，解决了流水线数据相关问题，采用延迟转移法，解决了流水线控制相关问题。论文设计了流水线演示系统，实现了流水线演示及效果分析的功能。最后，编写了测试程序，在FPGA平台上对流水线CPU进行了功能验证，并分析了流水效果，CPU运行正常，功能完备，取得了预期的结果。
[Abstract]:At present, most of the computer composition of the experimental platform in colleges and universities is pure hardware, the internal structure is fixed, flexibility is poor, which is not conducive to independent innovation of students. Greatly reduce the quality of teaching. FPGA technology provides a flexible design platform, this paper uses FPGA technology, designed 32-bit five-level pipeline CPU, can be used in the computer to form an experimental course. It helps to improve the quality of teaching. According to the actual needs, combined with the theoretical research, this paper puts forward the overall structure model of five-level pipeline CPU based on FPGA. The design process of 32-bit five-level pipeline CPU is completed by using DE2 development platform. The functional design of storing MEM and writing the result back to WB is presented, and the pipeline demonstration system is specially designed. The rationality of CPU design is verified by analyzing the effect of system demonstration. In this paper, the five cycles of pipeline CPU are designed by using Verilog HDL language, and the PC register and instruction memory are designed, and the instruction fetching function is realized. The decoding cycle includes the design of the controller CUand the register file and the decoding function of 20 instructions. The instruction execution cycle is mainly about the design of ALU, and the operation of data is realized. The storage cycle completes the design of the data storage, which is used to read and write the storage cycle. By designing multiplexer, the correct result can be written back to the destination register. Pipeline's design will inevitably bring related problems, including data correlation. Control correlation and structural correlation. This paper focuses on the first two kinds of correlation research and processing, design the internal forward push method and pause income method combined strategy, solve pipeline data related problems. The paper designs pipeline demonstration system and realizes the function of pipeline demonstration and effect analysis. Finally, a test program is written to verify the function of pipeline CPU on FPGA platform, and the result of income is analyzed.
【学位授予单位】：河北工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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