高性能DSP通信接口的研究与设计

发布时间：2018-01-19 11:04

本文关键词： DSP 串行通信接口地址预测功能验证覆盖率　出处：《江南大学》2013年硕士论文　论文类型：学位论文

【摘要】：数字信号处理技术已经在我们的生活中变得非常普及,其重要性在通信、语音和图像处理、航空航天、汽车电子等各个领域的应用中日益凸显。为了提供更快的处理速度和更为丰富的功能,系统集成化成为数字信号处理器(Digital Signal Processor, DSP)芯片的一个明确的发展趋势。为满足不同场合的应用,DSP芯片通常都集成了丰富的通信接口。通信接口作为DSP芯片与外界进行数据交换唯一通道,其性能也直接地影响了芯片的效率。本文在分析现在通用的各种串行通信接口(McBSP、I2C、SPI和USB)特点的基础上针对ZW100这款DSP芯片提出了一种新的uLink串行通信接口。uLink接口综合了以上几种的接口的一些特点,加入了全握手过程、自动数据模式、地址预测以及分时复用通道等功能,能有效地提高数据传输效率。并在数据帧中加入了传输目标地址,可以使数据接收方在数据接收过程中完全无需CPU的介入而将数据写入目标地址。整个uLink的设计采用了VLSI设计中自顶向下的设计方法,根据功能进行模块划分,利用硬件描述语言VHDL完成各个模块的RTL级描述。使用SYNOPSYS公司的仿真工具VCS对设计进行功能仿真,对仿真过程的覆盖率参数进行分析以保证验证结果的全面性和可靠性。以TSMC65纳米工艺为目标库,利用Design Compiler对设计RTL代码进行逻辑综合。对综合结果采用Formality进行形式验证,并用PrimeTime对综合结果进行设计时序验证。仿真和时序验证结果表明：整个设计实现了所有预期功能,满足uLink协议的所有要求。在500MHz的系统时钟下,uLink接口能够稳定地工作,其理论最高通信速率可达125Mbit/s。目前该接口已成功集成于ZW100这款32位定点DSP芯片中。
[Abstract]:Digital signal processing technology has been in our life has become very popular, and its importance in communication, voice and image processing, aerospace, automotive and other applications in various fields has become increasingly prominent. In order to provide faster processing speed and more functions, system integration has become a digital signal processor (Digital Signal Processor, DSP) a clear trend of chip. In order to meet the application of different occasions, usually DSP chip integrated rich communication interface. Communication interface as DSP chip for data exchange only channel with the outside world, its performance directly affects the efficiency of the chip.
Based on the analysis of current various serial communication interface (McBSP, I2C, SPI and USB) based on the characteristics of the DSP chip on the ZW100 proposed a new uLink serial communication interface.ULink interface integrated some characteristics above the interface, with full automatic handshake process, data model, forecast and address when the multiplex channel function, can effectively improve the efficiency of data transmission. And joined the transfer destination address in the data frame, the receiver can make the data in the data receiving process without the intervention of CPU and writes the data to the destination address.
The top-down design method in the design of VLSI uLink using the design of the whole, is divided into several modules according to function, RTL the use of hardware description language VHDL module is described. Using the SYNOPSYS simulation tool VCS function simulation of the design, comprehensive coverage and reliability of parameter simulation process are analyzed to ensure the verification results using TSMC65 nano technology. The target database, logic synthesis is applied to design RTL code using Design Compiler. The results of synthesis using Formality for formal verification, and the results of comprehensive design timing verification with PrimeTime.
Simulation and timing verification results show that the design and implementation of all the expected functions, meet all the requirements of uLink protocol. The 500MHz system clock, uLink interface can work stably, its theoretical maximum communication speed can reach 125Mbit/s. at the interface has been successfully integrated into the ZW100 32 bit fixed-point DSP.

【学位授予单位】：江南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7

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