基于训练方式的存储器时钟信号的自适应同步

发布时间：2018-01-19 20:44

本文关键词： 同步动态随机读写存储器延迟电路训练自适应　出处：《上海大学学报(自然科学版)》2015年04期 　论文类型：期刊论文

【摘要】：存储器是现代电子系统的核心器件之一,常用于满足不同层次的数据交换与存储需求.然而频率提高、时钟抖动、相位漂移以及不合理的布局布线等因素,都可能导致CPU对存储器访问稳定性的下降.针对同步动态随机读写存储器(synchronous dynamic random access memory,SDRAM)接口的时钟信号提出了一种自适应同步的训练方法,即利用可控延迟链使时钟相位按照训练模式偏移到最优相位,从而保证了存储器访问的稳定性.在芯片内部硬件上提供了一个可通过CPU控制的延迟电路,用来调整SDRAM时钟信号的相位.在系统软件上设计了训练程序,并通过与延迟电路的配合来达到自适应同步的目的:当CPU访问存储器连续多次发生错误时,系统抛出异常并自动进入训练模式.该模式令CPU在SDRAM中写入测试数据并读回,比对二者是否一致.根据测试数据比对结果,按训练模式调整延迟电路的延迟时间.经过若干次迭代,得到能正确访问存储器的延迟时间范围,即"有效数据采样窗口",取其中值即为SDRAM最优时钟相位偏移,完成训练后对系统复位,并采用新的时钟相位去访问存储器,从而保证读写的稳定性.仿真实验结果表明,本方法能迅速而准确地捕捉到有效数据采样窗口的两个端点位置,并以此计算出最佳的延迟单元数量,从而实现提高访问外部SDRAM存储器稳定性的目的.
[Abstract]:Memory is one of the core devices in modern electronic systems, which is often used to meet the different levels of data exchange and storage requirements. However, the frequency increase, clock jitter, phase shift and unreasonable layout and wiring factors. For synchronous dynamic random read and write memory. Synchronous dynamic random access memory. In this paper, an adaptive synchronization training method for clock signals in SDRAM interface is proposed, in which the clock phase is shifted to the optimal phase according to the training mode by using controllable delay chain. Thus, the stability of memory access is ensured, and a delay circuit controlled by CPU is provided on the internal hardware of the chip. Used to adjust the phase of SDRAM clock signal. The training program is designed on the system software. The purpose of adaptive synchronization is achieved by cooperating with the delay circuit: when the CPU accesses the memory continuously many times the error occurs. The system throws exceptions and automatically enters the training mode. This mode causes CPU to write test data in SDRAM and read back to compare the consistency of the two. Compare the results according to the test data. The delay time of the delay circuit is adjusted according to the training mode. After several iterations, the delay time range of the memory can be accessed correctly, that is, "effective data sampling window". Taking the median value as SDRAM optimal clock phase offset, the system is reset after the completion of the training, and a new clock phase is used to access the memory to ensure the stability of reading and writing. The simulation results show that. The method can quickly and accurately capture the two endpoint positions of the effective data sampling window and calculate the optimal number of delay units thus achieving the purpose of improving the stability of accessing external SDRAM memory.
【作者单位】：上海大学新型显示技术及应用集成教育部重点实验室;上海大学机电工程与自动化学院;
【基金】：国家自然科学基金资助项目(61376028) 上海市科委基金资助项目(13111104600)
【分类号】：TP333
【正文快照】： 在嵌入式系统中,随机读写存储器占有十分重要的地位.根据其工作原理,可以分为静态随机读写存储器(static random access memory,SRAM)和动态随机读写存储器(dynamicrandom access memory,DRAM).由于SRAM中存储单元的静态特性,其辅助电路较少、结构简单、速度较快,既可作为片上

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