基于节点预测的直接Cache一致性协议

发布时间：2018-01-22 01:15

本文关键词： 单芯片多处理器(CMP) 预测一致性协议目录可扩展　出处：《计算机学报》2014年03期 　论文类型：期刊论文

【摘要】：处理器性能的提升依赖于对存储系统性能的挖掘.随着片上集成内核数量的不断增大和特征尺寸的持续缩小,延迟、存储可扩展的Cache一致性协议已经成为提升访存效率的关键性因素.文中提出一种基于节点预测的直接Cache一致性协议-NPP协议,研究一致性交互延迟隐藏和目录存储开销减少技术.针对读、写缺失中存在的间接性问题和现有解决方案破坏已有数据局部性、无法获得最近数据副本等问题,分别提出节点挂起技术和直接写缺失处理技术,有效隐藏了目录访问延迟.为了实现准确的节点预测,作者还提出基于"签名"回收的历史信息更新算法,避免了冗余更新和不完整更新.使用SPLASH-2测试程序集,在基于2D MESH NoC互联的64核CMP下,相对于全映射目录协议,NPP协议的平均执行时间降幅为21.78%~31.11%;平均读缺失延迟降低14.22%~18.9%;平均写缺失延迟降低17.89%~21.13%.而获得上述性能提升的代价是网络流量平均增加6.62%~7.28%.
[Abstract]:The improvement of processor performance depends on the mining of storage system performance. With the increasing number of on-chip integrated cores and the continuous reduction of feature size, delay. The storage extensible Cache conformance protocol has become the key factor to improve the memory access efficiency. In this paper, a direct Cache conformance protocol-NPP protocol based on node prediction is proposed. Aiming at the indirect problem in reading and writing missing and the existing solutions which destroy the existing data locality and can not get the most recent data copy etc research on consistent interactive latency hiding and directory storage cost reduction. In order to realize accurate node prediction, the author also proposes an update algorithm of historical information based on "signature" recycling. Avoid redundant updates and incomplete updates. Using SPLASH-2 test assemblies, under 64-core CMP based on 2D MESH NoC interconnection, relative to the full-mapping directory protocol. The average execution time of NPP was 21.78% and 31.11% respectively. The average delayed reading loss decreased 14.2222% and 18.9%; The average write loss delay decreases 17.89% and 21.13%. The cost of achieving the above performance gains is an average increase in network traffic of 6.62% and 7.28%.
【作者单位】：中国航空工业集团公司西安航空计算技术研究所;西安交通大学电子与信息工程学院;
【基金】：国家“核高基”科技重大专项(2009ZX01039-003-001-03,2009ZX01023-004) 国家自然科学基金(60905007)资助~~
【分类号】：TP332
【正文快照】： 1引言良好的可扩展性和对芯片面积的高效利用促使CMP处理器(Chip Multi-Processor)被广泛使用.然而,芯片上连线的电气特性不可能与半导体工艺等比例缩放,线延迟问题已经成为未来CMP设计的重要限制因素[1-2].研究者提出延迟非一致的Cache访问(Non-Uniform Cache Access,NUCA)[3

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