电荷俘获型存储器模型及模拟研究

发布时间：2018-01-25 23:39

本文关键词： 电荷俘获型存储器模型模拟　出处：《兰州大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着非挥发存储器进入20nm工艺节点,传统的基于多晶硅浮栅结构的存储器在结构性能上遇到很多限制,其中最重要的问题是由于器件可靠性导致的尺寸无法按照等比例缩小的原则继续推进。为此,研究者们提出了多种新的挥发存储器结构,具有擦写速度快、可靠性高、制作工艺简单、成本低、与传统CMOS工艺完全兼容等优点的电荷俘获存储器以其分立存储的特性,成为多晶硅浮栅结构的最有潜力的替代方案之一。然而,目前电荷俘获存储器的研究中仍有许多问题需要解决。本论文首先回顾了非挥发性浮栅存储器的工作原理以及其在可微缩化发展上所面临的挑战,提出电荷俘获存储器的产生背景、发展历程以及工作原理。通过对电荷俘获存储器各功能层研究进展的分析和总结,指出了目前研究中存在的问题以及可能的解决方案。论文对基于氮化硅存储层的电荷俘获型存储器中涉及到的物理机理及物理模型,包括衬底电子进入存储层的各种隧穿方式、存储层陷阱能级在实空间和能量空间上的分布、电荷在存储层材料(氮化硅)中的迁移率、电荷的俘获及释放过程等做了详细分析,并在模拟过程中做了针对性的选择或处理。器件在编程和擦除操作时隧穿氧化层中的电场较大,通过陷阱辅助隧穿进入存储层的几率较小,在模拟中可不需考虑。在存储层陷阱能级的分布上,实验报道的能级分布有高斯分布、指数分布等等,但其分布的能级范围都很窄,所以可将其看作是单一的能级分布。对于被俘获的电荷从陷阱能级中的释放过程(机理),结合两性陷阱模型与Poole-Frenkel效应,本文对此做了详细的分析与讨论,给出了一种较为合理的模型解释,并将其用于数值模拟。将上述涉及到的模型方程加入电荷在存储层中输运的漂移-扩散方程和电流连续性方程中,形成耦合的方程组,通过对存储层网格化的方法将其离散,并利用牛顿迭代的方法对方程组进行求解,模拟了存储器的编程、擦除特性以及数据保持特性。本论文也研究了功能层厚度、陷阱参数等对器件特性的影响。SONOS结构存储器的编程速度随着隧穿层的厚度的增加而下降,但在隧穿层与阻挡层总的厚度不变的情况下,改变隧穿层的厚度对器件的编程速度没有影响；而对于TANOS结构,增大阻挡层的厚度并没有对器件的数据保持特性带来很大的改善,这验证了隧穿氧化层是数据保持状态下电荷泄漏的主要途径。对于文献中给出的不同的陷阱能级深度,我们对其编程和擦除特性进行了模拟,结果发现编程速度几乎没有变化,而擦除速度随着陷阱能级深度的减小而增加,主要的原因应该是更浅的陷阱能级深度导致了擦除时存储层陷阱中电荷释放到导带的数量增加。
[Abstract]:With the non-volatile memory entering the 20nm process node, the traditional memory based on the polysilicon floating gate structure has many limitations on the performance of the structure. The most important problem is that the size of the device can not be reduced according to the principle of equal proportion. Therefore, researchers have proposed a variety of new volatile memory structures, which have high speed of erasing. The charge-trapping memory, which has the advantages of high reliability, simple fabrication process, low cost and compatible with the traditional CMOS process, has the characteristics of discrete storage. It has become one of the most promising alternatives to polysilicon floating gate structure. However, there are still many problems to be solved in the research of charge capture memory. In this paper, the working principle of non-volatile floating gate memory and the challenges it faces in the development of scalable floating gate memory are reviewed, and the background of charge capture memory is proposed. Based on the analysis and summary of the research progress of the charge capture memory function layer, the existing problems and possible solutions are pointed out. The physical mechanism and physical models involved in charge capture memory based on silicon nitride storage layer, including various tunneling modes of substrate electrons entering the memory layer, are discussed in this paper. The distribution of trap energy levels in real space and energy space, the mobility of charge in storage layer material (silicon nitride), the capture and release process of charge are analyzed in detail. The electric field in the oxide layer of tunneling is larger during programming and erasure operation, and the probability of tunneling into the storage layer through trap assisted tunneling is small. There is no need to consider in the simulation. In the storage layer trap level distribution, the experimental energy level distribution includes Gao Si distribution, exponential distribution and so on, but the energy level distribution range is very narrow. Therefore, it can be regarded as a single energy level distribution. For the release process of trapped charge from trap level (mechanism, combined with amphoteric trap model and Poole-Frenkel effect). This paper makes a detailed analysis and discussion, gives a more reasonable model explanation, and applies it to numerical simulation. The model equations mentioned above are added to the drift-diffusion equation and the current continuity equation of charge transport in the storage layer to form the coupled equations and to discretize them by gridding the storage layer. Newton iterative method is used to solve the equations, and the memory programming, erasure characteristics and data retention characteristics are simulated. This thesis also studies the influence of the thickness of function layer and trap parameters on the device characteristics. The programming speed of SONOS structure memory decreases with the increase of tunneling layer thickness. However, when the total thickness of the tunneling layer and the barrier layer is constant, changing the thickness of the tunneling layer has no effect on the programming speed of the device. For the TANOS structure, increasing the thickness of the barrier layer does not improve the data retention characteristics of the device. This verifies that the tunneling oxide layer is the main way of charge leakage in the data holding state. For the different trap energy levels given in the literature, we simulate its programming and erasure characteristics. The results show that the programming speed is almost unchanged, and the erasure speed increases with the decrease of trap level depth. The main reason is that the shallow trap level depth leads to an increase in the amount of charge released to the conduction band in the storage trap during erasure.
【学位授予单位】：兰州大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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