基于FPGA的1553B总线接口设计与验证

发布时间：2018-01-31 15:28

本文关键词： B总线接口现场可编程门阵列光纤　出处：《现代电子技术》2015年03期 　论文类型：期刊论文

【摘要】：为降低成本,提高设计灵活性,提出一种基于FPGA的1553B总线接口方案;采用自顶向下的设计方法,在分析1553B总线接口工作原理和响应流程的基础上,完成了接口方案各FPGA功能模块设计;对关键模块编写VHDL代码,并采用Active-HDL软件进行了仿真;以Virtex-5 FPGA开发板和PC机为验证平台,在FPGA中分别模拟BC与RT,在PC机指令下进行了BC与RT功能模块间的收发测试,结果表明系统能在协议规定的1 MHz数据率下稳定运行;同时,为提升接口性能,采用光纤代替传统电缆传输介质,利用FPGA内嵌Rocket IO内核进行了传统1553协议数据的光纤传输,速率可达3 Gb/s以上。
[Abstract]:In order to reduce the cost and improve the design flexibility, a 1553B bus interface scheme based on FPGA is proposed. On the basis of analyzing the working principle and response flow of 1553B bus interface, the design of each FPGA function module of the interface scheme is completed by adopting the top-down design method. The VHDL code is written for the key modules, and the simulation is carried out with Active-HDL software. Using Virtex-5 FPGA development board and PC as the verification platform, the BC and RT modules are simulated in FPGA, and the transceiver test between BC and RT function modules is carried out under the instruction of PC. The results show that the system can run stably at the 1 MHz data rate specified in the protocol. At the same time, in order to improve the performance of the interface, optical fiber instead of the traditional cable transmission medium, using the FPGA embedded Rocket IO core for the traditional 1553 protocol data transmission. The rate can reach more than 3 Gb/s.
【作者单位】：上海航天电子技术研究所;
【分类号】：TN791;TP336
【正文快照】： 0引言MIL-STD-1553B[1](数字式时分制命令/响应型多路传输数据总线)由美国国防部于20世纪70年代末提出,它采用曼彻斯特编码方式和冗余的总线型拓扑结构,具有非常好的时钟同步能力及容错机制,极大地简化了电子设备之间的互联,因而被广泛应用于对可靠性要求较高的军事、航空、航

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