一种高性能DSP中断系统的研究与设计

发布时间：2018-02-01 15:02

本文关键词： 中断系统数字信号处理器中断向量表中断优先级外围设备控制处理器　出处：《江南大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着我国电子信息产业的发展,数字信号处理器(DSP)在军用和民用领域取得了越来越广泛的应用。巨大的市场压力使得DSP朝着高性能、低功耗的方向迈进。由于DSP内核和外设的通讯是依靠中断系统来完成的,因此中断系统的优劣己经成为了影响DSP性能的重要因素之一本论文在分析传统中断系统的基本结构及工作原理的基础上,设计并实现了一种高性能DSP中断系统。此中断系统拥有两个中断处理器,最大支持255个优先级,其中断向量表的中断服务例程可跨越且中断优先级可分组。在实际应用中优先级和仲裁时间可灵活设置,使得中断源被合理分配,减少了DSP在中断处理上的消耗,提高了DSP内核的运算效率。本论文设计的中断系统由服务请求商、服务请求节点(SRN)、中断控制单元(ICU和PICU)、两根中断仲裁总线和中断服务提供商五部分组成。本中断系统的两个中断服务提供商分别为DSP和外围设备控制处理器(PCP),它们共同处理服务请求商发出的中断服务请求；服务请求商一般指需要申请中断的外设(包括DSP和PCP本身)；外设通过与自身相连的一个或多个服务请求节点向中断服务提供商申请中断服务请求,服务请求节点通过可选的DSP中断仲裁总线或者PCP中断仲裁总线将中断服务请求发送到对应的中断控制单元(ICU或PICU)；中断控制单元负责仲裁收到的服务请求,确定拥有最高优先级的中断服务请求,并向对应的DSP或者PCP生成中断请求；最后DSP或者PCP响应并处理中断。利用硬件描述语言VHDL对中断系统进行了RTL级的描述,采用SYNOPSYS公司的仿真软件VCS在系统层次上对各种不同的中断事件进行了时序验证。结果表明,中断系统的设计达到了预期要求；在高频DSP系统中,在仲裁周期上可节省2到6个时钟周期,提高了系统效率。此中断系统己运用于一款DSP芯片中并成功投入市场。
[Abstract]:With the development of electronic information industry in China, digital signal processor (DSP) has been more and more widely used in military and civilian fields. Since the communication between DSP kernel and peripheral devices depends on interrupt system, the quality of interrupt system has become one of the important factors that affect the performance of DSP. On the basis of analyzing the basic structure and working principle of the traditional interrupt system, this paper designs and implements a high-performance DSP interrupt system, which has two interrupt processors. The maximum support is 255 priority, in which interrupt service routine can cross and interrupt priority can be grouped. In practical application, priority and arbitration time can be set flexibly, so interrupt source can be allocated reasonably. The consumption of DSP in interrupt processing is reduced, and the efficiency of DSP kernel is improved. The interrupt system designed in this paper is composed of service requester, service request node, interrupt control unit, ICU and PICU). The two interrupt arbitration bus and the interrupt service provider are composed of five parts. The two interrupt service providers of the interrupt system are DSP and peripheral equipment control processor (DSP). They jointly process service interruption requests from service requesters; Service requesters generally refer to peripherals (including DSP and PCP themselves) that need to apply for interruptions; The peripheral applies to an interrupt service provider for an interrupt service request through one or more service request nodes connected to itself. The service request node sends the interrupt service request to the corresponding interrupt control unit (ICICU) or PICUU via the optional DSP interrupt arbitration bus or the PCP interrupt arbitration bus. The interrupt control unit is responsible for arbitrating the received service request, determining the interrupt service request with the highest priority, and generating the interrupt request to the corresponding DSP or PCP. Finally, DSP or PCP responds and handles interruptions. The hardware description language VHDL is used to describe the interrupt system at RTL level. The simulation software VCS of SYNOPSYS Company is used to verify the timing of different interrupt events at the system level. The results show that the design of the interrupt system meets the expected requirements. In high frequency DSP system, two to six clock cycles can be saved in the arbitration cycle, and the system efficiency is improved. The interrupt system has been used in a DSP chip and successfully put into the market.
【学位授予单位】：江南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

【参考文献】