基于FPGA的数字射频存储器的设计与应用

发布时间：2018-02-04 07:35

本文关键词： 数字射频存储器现场可编程门阵列低压差分信号幅度量化 DSP　出处：《北京工业大学》2012年硕士论文　论文类型：学位论文

【摘要】：现代化雷达（Radar）系统的重要组件是数字射频存储器（Digital RadioFrequency Memory DRFM），它能够存储、传输和处理射频信号及微波信号。现代化雷达（Radar）通常运用脉压、对相位进行编码等较为复杂的数字信号处理技术，由于DRFM是这些数字信号处理技术的佼佼者，所以其的作为RF频率源在电子战领域的应用越来越广泛的应用。今天，DRFM技术在国内处于起步阶段，与国外，DRFM的各项指标：采样率、动态范围和采样精度等方面还不能达到现代化雷达对数字信号处理的要求。本文介绍了数字射频存储器的工作原理、幅度量化类型、基本组成和典型应用，在目前研究成果的基础之上给出了便于工程应用的设计方案，将基于现场可编程门阵列（Field Programmable GateArray FPGA）所实现的幅度量化成功应用于此方案中。本文具体研究了DRFM数据采集模块的设计，DRFM数据存储模块的设计，LVDS在DRFM中的应用以及数字信号处理算法及仿真。本方案采用双通道采样率为500MHz的ADC并行交替等效采样以达到1GHz采样率，采样精度为12位。相干检波的数字正交技术的实现可以将信号复包罗的全部信息保存下来。DRFM的控制模块由单片机（Microprogrammed Control Unit MCU）、DSP（Digital Signal Processor）实现，多路采样数据缓冲器由现场可编程门阵列器件实现，FPGA的编程使用硬件描述语言（VHDL），同时可以实现布线的时序仿真和功能分析。本方案中低压差分信号（LVDS）芯片的大量使用，使系统的功耗得以降低，系统的可靠性得到了提高。在本文的最后，，通过软件对数字信号处理算法进行了仿真，证明了本方案的可行性。本文对比了基于专用FIFO芯片和基于FPGA的DRFM系统模块的优劣，说明了基于FPGA的DRFM系统模块具有更高的性能指标。
[Abstract]:The important component of the modern radar radar system is Digital RadioFrequency Memory DRFM, which can be stored. Transmitting and processing radio frequency signal and microwave signal. Modern radar radar usually uses pulse compression, phase coding and other more complex digital signal processing technology. Because DRFM is one of the best digital signal processing technology, it is widely used as RF frequency source in the field of electronic warfare. Today, DRFM technology is in its infancy in China. Compared with the foreign DRFM such as sampling rate, dynamic range and sampling precision, it can not meet the requirement of digital signal processing in modern radar. In this paper, the working principle, amplitude quantization type, basic composition and typical application of digital RF memory are introduced. Based on the current research results, the design scheme for engineering application is given. Will be based on Field Programmable Gate Array Field Programmable GateArray FPGA). The realization of amplitude quantization is successfully applied in this scheme. The design of DRFM data acquisition module is studied in detail in this paper. The design of DRFM data storage module. The application of LVDS in DRFM and the digital signal processing algorithm and simulation. In this scheme, the parallel equivalent sampling of 500MHz dual-channel ADC is used to achieve 1GHz sampling rate. The precision of sampling is 12 bits. The realization of digital orthogonal technique of coherent detection can save all the information of signal complex inclusion. The control module of DRFM can be controlled by single chip computer (. Microprogrammed Control Unit MCU. DSP(Digital Signal Processor. the multiplex sampling data buffer is realized by field programmable gate array device. The programming of FPGA is based on the hardware description language VHDL, and it can realize the timing simulation and function analysis of the wiring at the same time. In this scheme, the low voltage differential signal (LVDS) chip is widely used. The power consumption of the system is reduced and the reliability of the system is improved. At the end of this paper, the digital signal processing algorithm is simulated by software, and the feasibility of the scheme is proved. This paper compares the advantages and disadvantages of the special FIFO chip and the DRFM system module based on FPGA, and explains that the DRFM system module based on FPGA has higher performance index.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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