嵌入式处理器取指单元关键部件低功耗技术研究

发布时间：2018-02-05 03:06

本文关键词： 取指单元低功耗指令高速缓存分支目标缓存路预测循环过滤分支跟踪　出处：《浙江大学》2012年硕士论文　论文类型：学位论文

【摘要】：低功耗是嵌入式处理器的主要研究方向,而取指单元包含大量存储器访问,其功耗已经成为整个处理器功耗的重要组成部分。本文重点研究了嵌入式处理器取指单元关键部件的低功耗技术。这些创新技术的应用能够使嵌入式CPU在保持处理器性能的基础上,有效降低取指单元动态功耗。本文的主要内容及创新点包括： 1、基于指令历史链接关系的路预测高速缓存低功耗技术。本文提出了一种基于分支目标缓存(BTB)复用和跳转历史链接关系表的两级跳转路预测架构,以极低的硬件成本解决了分支目标指令所在行的冲突问题,提高了跳转预取路预测的准确率,进而有效降低了指令Cache的动态功耗。 2、基于循环体访问过滤的分支目标缓存低功耗技术。针对循环体内指令对BTB访问产生的冗余功耗问题,本文提出了一种循环体访问过滤机制,消除循环体指令流中顺序指令对BTB的无效访问；进一步提出了一种分支跟踪方法补偿由于循环过滤机制对循环体中非循环类分支指令的错误过滤造成的性能损失。这两种技术在保障处理器性能的基础上降低了BTB的动态功耗。本文提出的低功耗技术设计简单、硬件成本低,对嵌入式处理器取指单元低功耗设计具有积极意义。
[Abstract]:Low power consumption is the main research direction of embedded processor, and the fetch cell contains a large number of memory access. The power consumption of embedded processor has become an important part of the whole processor power. This paper focuses on the low power technology of the key components of the embedded processor. The application of these innovative technologies can enable embedded CPU to be guaranteed in the embedded system. Based on processor performance. The main contents and innovations of this paper are as follows: 1. Low power technology of path prediction cache based on instruction history link relationship. In this paper, a two-level hopping path prediction architecture based on branch target buffer (BTB) multiplexing and hopping history link relation table is proposed. The collision problem of the line of branch target instruction is solved with very low hardware cost, and the accuracy of jump prefetching prediction is improved, and the dynamic power consumption of instruction Cache is reduced effectively. 2. Low power consumption technology of branch target buffer based on cyclic body access filtering. Aiming at the redundant power consumption of BTB access caused by loop body instruction, this paper proposes a cyclic volume access filtering mechanism. Eliminating invalid access to BTB by sequential instructions in the flow of circular body instructions; Furthermore, a branch tracking method is proposed to compensate for the performance loss caused by the error filtering of the loop filter mechanism on the non-cyclic branch instructions of the loop body. These two techniques can reduce the processor performance on the basis of ensuring the processor performance. The dynamic power consumption of BTB. The low power technology proposed in this paper has the advantages of simple design and low hardware cost, which is of great significance to the low power design of the embedded processor.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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