数字视频接口（DVI）发送器的设计与实现

发布时间：2018-02-08 10:28

本文关键词： 数字视频接口最小转换差分信号电荷泵锁相环并串转换 T.M.D.S.驱动版图　出处：《国防科学技术大学》2013年硕士论文　论文类型：学位论文

【摘要】：DVI（Digital Visual Interface，数字视频接口）作为一种优秀接口标准的提出，满足了人们对显示设备高分辨率和高刷新率的要求。相对于传统的模拟显示设备，其稳定性和显示性能得到了加强，而且更进一步地降低了平板显示器的成本。DVI接口已经成为当今数字显示技术中广泛采用的接口之一。本文以DVI接口通讯协议为基础，详细介绍并分析其基本电气链接—TMDS（Transition Minimized Differential Signaling，最小转换差分信号）技术，，成功设计并实现了一款用于DVI接口发送器的物理层电路。为满足DVI1.0标准的要求，该电路输入时钟信号频率在：25MHz~165MHz，链路高速串行数据传输速率在：250Mbps~1.65Gbps。为解决输入信号频率范围宽、数据传输速率高等问题，本文主要做出了如下几个方面的研究与创新： 1、深入研究DVI1.0协议规范，对DVI发送器进行系统结构定义和功能模块划分。 2、设计一种用于产生时钟信号十倍频的电荷泵锁相环。在进行锁相环数学模型分析的基础上，应用Simulink工具建模仿真，为后续各个模块的参数设定提供理论指导。改进了本文的电荷泵电路，采用“自举电路”消除锁相环非理想效应中电荷共享等问题；改进了三级环形压控振荡器电路，采用交叉耦合式延迟单元产生快速理想的全摆幅差分输出。仿真结果表明，输入信号在频率范围25MHz~165MHz条件下，锁相环电路均能正常工作，且锁定时间均小于2μs，噪声抖动测试峰-峰值抖动均小于2.5%。 3、设计一款用于高速串行数据传输的驱动器电路。对比各接口标准电路结构，提出简化的电流模主体驱动电路，实现了满足DVI1.0协议要求的低摆幅（400mV~600mV）差分信号传输，链路带宽达到1.65GHz，满足设计要求。改进了电平转换电路，实现从内核电路1.2V电压域到外部传输电路3.3V电压域的转换，降低了电磁干扰对传输信号的影响，很好地满足高频信号传输的需要。 4、采用SMIC0.11μm、1P8M（单层多晶硅八层金属）、1.2V/3.3V混合信号CMOS工艺，完成整体电路的版图设计，芯片面积为121.66μm116.16μm。
[Abstract]:As an excellent interface standard, DVI(Digital Visual Interface (Digital Video Interface) meets the requirements of high resolution and high refresh rate of display devices. Compared with traditional analog display devices, its stability and performance are enhanced. Furthermore, it reduces the cost of flat panel display. DVI interface has become one of the widely used interfaces in digital display technology. Based on the DVI interface communication protocol, this paper introduces and analyzes the basic electrical link (TMDS transition Minimized Differential signaling) technology in detail. A physical layer circuit for DVI interface transmitter is successfully designed and implemented. In order to meet the requirements of DVI1.0 standard, the clock signal frequency of the circuit is at: 25MHz / 165MHz, and the link high-speed serial data transmission rate is at: 250Mbps1.65Gbps.In order to solve the problem, the input signal frequency range is wide. High data transmission rate, this paper mainly made the following aspects of research and innovation:. 1. Deeply study the DVI1.0 protocol specification, define the system structure and partition the function module of the DVI transmitter. 2. A charge pump phase-locked loop (CPPLL), which is used to generate clock signal 10 times frequency, is designed. Based on the mathematical model analysis of PLL, the Simulink tool is used to model and simulate the PLL. This paper improves the charge pump circuit in this paper, adopts "bootstrap circuit" to eliminate the problem of charge sharing in the non-ideal effect of phase-locked loop, and improves the three-stage ring voltage-controlled oscillator circuit. A fast and ideal full swing differential output is generated by cross-coupled delay unit. The simulation results show that the input signal can work normally in the frequency range of 25MHz / 165MHz. The locking time is less than 2 渭 s, and the peak to peak jitter of noise jitter is less than 2.5 渭 s. 3. A driver circuit for high speed serial data transmission is designed. Compared with the standard circuit structure of each interface, a simplified current-mode main driver circuit is proposed to realize the differential signal transmission with low swing of 400mV / 600mV, which meets the requirements of DVI1.0 protocol. The link bandwidth reaches 1.65 GHz, which meets the design requirements. The level conversion circuit is improved to realize the conversion from 1.2 V voltage domain of the core circuit to 3.3 V voltage domain of the external transmission circuit, which reduces the influence of electromagnetic interference on the transmission signal. It can meet the needs of high frequency signal transmission. 4. The SMIC0.11 渭 m 1P8M (single layer polysilicon 8-layer metal / metal / 1.2V / 3.3V mixed signal CMOS process) is used to complete the layout design of the whole circuit. The chip area is 121.66 渭 m 116.16 渭 m.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7

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