基于FPGA的通用总线动态可重构设计

发布时间：2018-02-10 01:52

本文关键词： 通用总线动态局部可重构 EAPR 嵌入式开发内部配置访问端口　出处：《南京航空航天大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着微电子技术的迅速发展,现代测试系统正在向通用系统的方向发展,因此,测试系统必须具有通用化和可扩展性等一系列优点。总线是测试系统的重要组成部分,针对此研究热点,本文开发了一套基于FPGA的通用总线动态可重构系统,实现了多种总线通信功能的实时切换。本文首先分析了数据通信总线测试系统的国内外研究现状,根据通用化的发展方向,给出了数据通信总线测试系统的总体设计方案,并设计上位机监控界面和相应总线的外围接口电路。分析不同总线的通信协议,利用FPGA的可编程特性分别设计了ARINC 429、RS232、RS422和CAN总线等多个通信模块,并进行功能仿真和波形的具体分析。然后结合基于EAPR的动态局部重构方法和基于FPGA的嵌入式开发流程,在FPGA芯片中手动规划动态局部可重构区域,设计了一个总线通信可重构系统,从硬件处理器系统设计、应用软件设计和动态局部可重构设计等方面详细分析了该系统的设计和实现流程。把上位机界面、FPGA中内嵌的微处理器和内部配置访问端口ICAP相结合,可以从外部的CF卡中实时加载不同的总线通信模块,以小规模的硬件资源实现了大规模系统的功能。最后在FEM025开发板上进行功能验证,实验结果表明,本文所设计的系统各项通信指标满足要求,界面友好,操作简单,具有很高的实用价值。
[Abstract]:With the rapid development of microelectronic technology, modern test system is developing to the direction of universal system. Therefore, test system must have a series of advantages, such as generalization and extensibility. Bus is an important part of test system. In this paper, a dynamic reconfigurable bus system based on FPGA is developed, which realizes real-time switching of various bus communication functions. Firstly, this paper analyzes the research status of data communication bus testing system at home and abroad. According to the general development direction, the overall design scheme of the data communication bus test system is given, and the monitor interface of the upper computer and the peripheral interface circuit of the corresponding bus are designed, and the communication protocols of different buses are analyzed. Based on the programmable characteristic of FPGA, several communication modules, such as ARINC 429 / RS232 / RS422 and CAN bus, are designed, and the function simulation and waveform analysis are carried out. Then, the dynamic local reconstruction method based on EAPR and the embedded development flow based on FPGA are combined. A bus communication reconfigurable system is designed by manually planning the dynamic local reconfigurable region in the FPGA chip, and the hardware processor system is designed. Application software design and dynamic local reconfigurable design are used to analyze the design and implementation of the system in detail. The microprocessor embedded in the upper computer interface is combined with the internal configuration access port (ICAP). Different bus communication modules can be loaded from the external CF card in real time, and the function of large-scale system can be realized with small scale hardware resources. Finally, the function verification is carried out on the FEM025 development board, and the experimental results show that, The system designed in this paper meets the requirements of communication, friendly interface, simple operation, and has high practical value.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP336;TN791

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