基于ARMv4指令集的32位RISC微控制器的设计与实现

发布时间：2018-02-11 13:25

本文关键词： 微控制器精简指令集计算机 ARM指令集片上系统片上总线　出处：《浙江理工大学》2013年硕士论文　论文类型：学位论文

【摘要】：嵌入式系统在很多领域有着广泛的应用，包括个人消费、通信、工业控制以及军事等。嵌入式系统的核心是微控制器，，其性能直接影响到整个系统的性能。本文基于开源IP核设计并实现了一款具备基本功能的微控制器，该微控制器用于一款小型射频SOC芯片。该微控制器的核心是一个基于ARMv4指令集微处理器内核，外围设备包括SPI控制器、通用串口、定时器、通用IO接口和外部中断以及中断控制器。本文设计的微处理器是在一款基于ARMv2a指令集架构的开源IP核的基础上，进行深度修改得到。ARM作为目前RISC（Reduced Instruction Set Computer），即精简指令集计算机的代表，在嵌入式领域有着广泛的应用，本文选择ARM指令集有着深远意义。本文设计的微处理器内核兼容ARMv4指令集48条指令中的43条，5条协处理器指令除外。该微处理器内核拥有三级流水线结构和Wishbone系统总线，而且能够很好的兼容现有编译器，方便应用调试。外围设备也是微控制器的重要组成部分，微处理器影响着微控制器的性能，而外围设备则关系到整个微控制器功能的丰富性。本文设计的微控制器包括了五个外围设备，其中SPI控制器和通用串口是参考现有案例自主重点设计，定时器、通用IO接口及外部中断和中断控制器只具备简单功能，为满足射频SOC基本需求而设置。SPI控制器符合SPI通信协议标准；通用串口具有最基本的数据帧结构，即1位起始位、8位宽的数据位、没有校验位，停止位位2位。所有外设都基于Wishbone系统总线从设备而设计，不仅应用于本文的微控制器，还可以应用于其他任何基于Wishbone系统总线的设计。仿真验证是数字系统设计的重要流程，包括功能仿真和布局布线后的仿真。本文设计的微控制器从整体到各个功能模块都进行了完整的仿真，功能仿真所使用的仿真工具是Modelsim6.5f版本；由于没有目标工艺库，因此布局布线后的仿真是针对Altera公司的CycloneII系列FPGA进行的。通过最后微控制器在FPGA上的测试，证明整个设计实现了完整的微控制器功能，能够满足射频SOC对微控制器的需求。
[Abstract]:Embedded systems are widely used in many fields, including personal consumption, communication, industrial control, military and so on. The core of embedded system is microcontroller. Its performance directly affects the performance of the whole system. This paper designs and implements a microcontroller with basic functions based on open source IP core. The microcontroller is used in a small RF SOC chip. The core of the microcontroller is a microprocessor kernel based on ARMv4 instruction set. The peripheral devices include SPI controller, universal serial port, timer, etc. General IO interface and external interrupt and interrupt controller. The microprocessor designed in this paper is based on an open source IP core based on ARMv2a instruction set architecture, and gets the. Arm as the representative of RISC(Reduced Instruction Set computer, which is widely used in embedded field. The selection of ARM instruction set in this paper is of far-reaching significance. The microprocessor kernel designed in this paper is compatible with 43 or 5 coprocessor instructions of the 48 instructions of the ARMv4 instruction set. The microprocessor core has a three-level pipeline structure and a Wishbone system bus. And can be very good compatible with the existing compiler, easy to apply debugging. The peripheral equipment is also an important part of the microcontroller. The microprocessor affects the performance of the microcontroller, and the peripheral device is related to the richness of the function of the whole microcontroller. The microcontroller designed in this paper includes five peripherals. The SPI controller and the general serial port are designed independently with reference to the existing cases. The timer, the general IO interface and the external interrupt and interrupt controller have only simple functions. In order to meet the basic requirements of RF SOC, the. SPI controller conforms to the standard of SPI communication protocol, the universal serial port has the most basic data frame structure, that is, 1 bit starting bit and 8 bit wide data bit, there is no check bit, All peripherals are designed based on Wishbone system bus slave device, which can be applied not only to the microcontroller in this paper, but also to any other design based on Wishbone system bus. Simulation verification is an important flow of digital system design, including function simulation and layout and routing simulation. The simulation tool used in functional simulation is the Modelsim6.5f version. Because there is no target process library, the simulation after layout and routing is done for Altera's CycloneII series FPGA. Finally, the microcontroller is tested on FPGA. It is proved that the whole design realizes the complete function of microcontroller and can meet the demand of RF SOC for microcontroller.
【学位授予单位】：浙江理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TN47

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