基于线程重组的GPGPU访存不规则问题微架构方案研究与验证

发布时间：2018-02-12 03:42

本文关键词： 通用图形处理器访存不规则性缓存竞争数据局部性微架构　出处：《东南大学》2016年硕士论文　论文类型：学位论文

【摘要】：近十年来,随着可编程性和计算能力的不断提升,GPU的应用范围已扩展至通用计算领域。众多通用计算GPU程序中包含访存不规则性。访存不规则性阻碍了GPU缓存对线程束内和线程束间数据局部性的捕获,使得程序执行速度低下。研究人员对GPU微架构进行了大量改进,以保护GPU程序中的数据局部性。但现有技术尚不能有效保护访存不规则程序中的线程束间数据局部性。为此,本文设计了基于线程重组的线程束间数据局部性保护方案。本文首先介绍了该线程重组方案包含的两项技术措施：(1)在线程束之间交换线程以避免线程束间的缓存竞争、保护数据局部性；(2)对访存流进行调整,以降低访存延时并提升访存不规则程序性能。接着,本文阐述了实现上述技术措施所需的GPU微架构修改,即引入重组缓冲区和修改发射逻辑。随后,本文分析了线程重组的性能开销,并讨论了减少开销的具体措施。最后,本文结合线程重组和一项线程束内数据局部性保护技术MRPB,设计了兼顾线程束间和线程束内数据局部性的综合方案。该微架构方案在GPU程序执行初期对其进行访存特征分析,根据程序特征分别采用线程重组和MRPB技术保护不同类型的数据局部性。本文在仿真平台GPGPU-Sim上分别实现了线程重组方案和综合方案,并使用以访存不规则程序为主的GPGPU测试集PolyBench对两者进行了验证。实验结果表明,与基准架构相比,线程重组方案使得一级缓存缺失平均减少28.2%,IPC平均提升44.9%。上述结果表明,本文设计的线程重组方案可以有效保护数据局部性,提升访存不规则程序的执行速度。此外,综合方案使得一级缓存缺失平均减少34.9%,IPC平均提升63.2%,这表明综合方案在线程重组方案基础上进一步保护了数据局部性,并提升了程序执行速度。
[Abstract]:In the last decade, With the continuous improvement of programmability and computing power, the application of GPUs has been extended to the field of general computing. Many common computing GPU programs include memory access irregularities, which hinder the GPU cache to thread bundles and. Capture of data locality between thread bundles, In order to protect the data localization in GPU program, the existing technology can not effectively protect the data localization between threads in irregular program. This paper designs a data locality protection scheme for thread bundles based on thread recombination. Firstly, this paper introduces two technical measures: 1) exchanging threads between thread bundles in order to avoid cache competition between thread bundles. To reduce the access delay and improve the performance of irregular access program, this paper describes the modification of GPU microarchitecture needed to implement the above technical measures. Then, this paper analyzes the performance overhead of thread reorganization, and discusses the specific measures to reduce the overhead. In this paper, combined with thread reconfiguration and a technique of data locality protection in thread bundles, a comprehensive scheme is designed, which takes account of data localization between thread bundles and within thread bundles. The microarchitecture is used to analyze the memory access characteristics of GPU programs at the early stage of execution. According to the characteristics of the program, thread recombination and MRPB technology are used to protect different types of data locality. In this paper, a thread recombination scheme and a comprehensive scheme are implemented on the simulation platform GPGPU-Sim, respectively. The experimental results show that compared with the benchmark architecture, the thread reorganization scheme can reduce the average loss of first-level cache by 28.2% and increase the average value by 44.9%. The threading reorganization scheme designed in this paper can effectively protect data locality and speed up the execution of irregular programs. The integrated scheme can reduce the average loss of the first-level cache by 34.9% and increase the IPC by 63.2 on average, which indicates that the integrated scheme can further protect the data locality and improve the speed of program execution on the basis of the thread-reconfiguration scheme.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP332

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